p87c770 ETC-unknow, p87c770 Datasheet - Page 16

• Manufacturer Part Number: p87c770
• Description: Microcontrollers Ntsc With On-screen Display Closed Caption
• Manufacturer: ETC-unknow

Philips Semiconductors
10.3
Table 10 Serial Control Register (SFR address D8H)
Table 11 Description of S1CON bits
1999 Jun 11
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
CR2
BIT
7
6
5
4
3
2
7
1
0
Serial Control Register (S1CON)
SYMBOL
ENS1
ENS1
STO
CR2
CR1
CR0
STA
AA
SI
6
Enable Serial I/O. When ENS1 = 0, the SIO is disabled and reset. The SDA and SCL
outputs are in a high-impedance state; P3.4 and P3.5 function as open-drain ports.
When ENS1 = 1, the SIO is enabled. The P3.4 and P3.5 port latches must be set to
logic 1.
START flag. When the STA bit is set in Slave mode, the SIO hardware checks the
status of the I
while the SIO is in Master mode, SIO transmits a repeated START condition.
STOP flag. With this bit set while in Master mode a STOP condition is generated. When
a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the
Slave mode, the STO flag may also be set to recover from an error condition. In this
case, no STOP condition is transmitted to the I
hardware behaves as if a STOP condition has been received and releases SDA and
SCL. The SIO then switches to the ‘not addressed’ slave receiver mode. The STO flag
is automatically cleared by hardware.
SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of
the following conditions:
Assert Acknowledge. When the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line when:
With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested
when the ‘own slave address’ or general call address is received.
Clock Rate selection. These three bits determine the serial clock frequency when SIO
is in Master mode; see Table 12. The maximum I
A START condition is generated in Master mode
Own slave address received during AA = 1
General call address received while S1ADR.0 = 1 and AA = 1
Data byte received or transmitted in Master mode (even if arbitration is lost)
Data byte received or transmitted as selected slave
STOP or START condition received as selected slave receiver or transmitter.
Own slave address is received
General call address is received (S1ADR.0 = 1)
Data byte received while device is programmed as a Master receiver
Data byte received while device is a selected Slave receiver.
STA
5
2
C-bus and generates a START condition if the bus is free. If STA is set
STO
4
16
SI
3
DESCRIPTION
2
C-bus interface. However, the SIO
2
AA
C-bus frequency is 400 kHz.
2
P8xCx70 family
CR1
1
Product specification
CR0
0