p87c770 ETC-unknow, p87c770 Datasheet - Page 25

• Manufacturer Part Number: p87c770
• Description: Microcontrollers Ntsc With On-screen Display Closed Caption
• Manufacturer: ETC-unknow

Philips Semiconductors
11.5
11.5.1
The BUSY signal can generate an interrupt (PX7) to the CPU if enabled by IEN1.5, the vector address is 0063H. This
register is used to enable/disable the BUSY interrupt and the Watchdog Timer.
Table 32 BUSY interrupt and Watchdog Control Register (SFR address EBH)
Table 33 Description of the BWC bits
11.5.2
RBUSY is bit 5 of the SFR IRQ1 (address 98H). A falling edge of the active BUSY signal generates a pending interrupt
to the CPU and forces the RBUSY bit HIGH. In the service routine, this bit should be cleared before returning to the main
routine. As long as RBUSY is HIGH, a pending interrupt is always present. Each time BUSY is activated by a falling edge,
the RBUSY is set HIGH. If the interrupt is not served by the next falling BUSY edge, then RBUSY is written to HIGH again
and no error of overrun is indicated.
1999 Jun 11
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
7 to 2
BIT
7
1
0
Busy interrupt and Watchdog Timer control
BUSY
I
NTERRUPT
INTERRUPT AND
SYMBOL
BUSY
R
EW
6
EQUEST
(RBUSY)
These 6 bits are not used.
Enable Watchdog Timer. If EW = 0, then the Watchdog Timer is disabled. If EW = 1,
then the Watchdog Timer is enabled and the Power-down mode is disabled.
When BUSY = 0, an active external interrupt will generate an interrupt to the CPU.
When BUSY = 1, external interrupts are disabled.
It is not recommended to update the display RAM when the BUSY signal is active
(LOW), due to the effect it may have on the OSD display. The display RAM can be
updated when the BUSY signal is inactive.
W
ATCHDOG
5
C
ONTROL
4
R
EGISTER
25
(BWC)
3
DESCRIPTION
2
P8xCx70 family
EW
1
Product specification
BUSY
0