z8f083a ZiLOG Semiconductor, z8f083a Datasheet - Page 39
z8f083a
Manufacturer Part Number
z8f083a
Description
High-performance 8-bit Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8F083A.pdf
(256 pages)
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PS026308-1207
Internal RESET
System Clock
Note: Not to Scale
WDT Clock
VDD = 3.3 V
signal
Watchdog Timer Reset
External Reset Input
V
V
POR
VBO
If the device is in NORMAL or STOP mode, the WDT initiates a system reset at time-out
if the WDT_RES Flash option bit is programmed to 1. This is the unprogrammed state of
the WDT_RES Flash option bit. If the bit is programmed to 0, it configures the WDT to
cause an interrupt, not a system reset, at time-out. The WDT status bit in the reset status
(RSTSTAT) register is set to 1to signify that the reset was initiated by the WDT.
The RESET pin has a schmitt-triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the system reset sequence. Because of the possible asynchronicity of the system
clock and reset signals, the required reset duration may be three or four clock periods. A
reset pulse of three clock cycles in duration might trigger a reset and a reset pulse of four
cycles in duration always triggers a reset.
While the RESET input pin is asserted low, the Z8 Encore! F083A Series devices remain
in the Reset state. If the RESET pin is held low beyond the system reset time-out, the
Execution
Program
Figure 7. Voltage Brown-Out Reset Operation
Brownout
Voltage
counter delay
POR
Z8 Encore!
Reset and Stop Mode Recovery
Product Specification
Execution
Program
®
F083A Series
VDD = 3.3 V
27
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