z8pe003 ZiLOG Semiconductor, z8pe003 Datasheet - Page 18

• Manufacturer Part Number: z8pe003
• Description: Feature-enhanced Z8plus 1k Rom One-time Programmable Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

Z8PE002
Z8Plus OTP Microcontroller
INTERRUPT SOURCES
Table 10 presents the interrupt types, sources, and vectors
available in the Z8Plus. Other processors from the Z8Plus
family may define the interrupts differently.
External Interrupt Sources
External sources can be generated by a transition on the cor-
responding port pin. The interrupt may detect a rising edge,
a falling edge, or both.
Notes: The interrupt sources and trigger conditions are device
Internal Interrupt Sources
Internal interrupt sources and trigger conditions are device
dependent. On-chip peripherals may set interrupt under var-
ious conditions. Some peripherals always set their corre-
sponding
figured to do so.
See the device product specification to determine available
sources, triggering edge options, and exact programming
18
Name
IREQ
IREQ
IREQ
IREQ
IREQ
IREQ
IREQ
0
1
2
3
4
5
6
–IREQ
dependent. See the device product specification to de-
termine available sources (internal and external), trig-
gering edge options, and exact programming details.
Although interrupts are edge triggered, minimum inter-
rupt request Low and High times must be observed for
proper operation. See the device product specification
for exact timing requirements on external interrupt re-
quests (
IREQ
15
T
bit while others must be specifically con-
W
IL
,
T
W
IH
Sources
Timer0 Time-out
PB4 High-to-Low
Transition
Timer1 Time-out
PB2 High-to-Low
Transition
PB4 Low-to-High
Transition
Timer2 Time-out
Reserved
).
Table 10. Interrupt Types, Sources, and Vectors
Vector Location
2,3
4,5
6,7
8,9
A,B
C,D
P R E L I M I N A R Y
details. For more details on the interrupt sources, refer to
the chapters describing the timers, comparators, I/O ports,
and other peripherals.
Interrupt Mask Register (IMASK) Initialization
The
ables the interrupts (Table 11). When bits
set to
Bit
the individual interrupt requests can be recognized. Reset-
ting bit
reset by the
0
the execution of an Interrupt Return (
IMASK
Notes: It is not good programming practice to directly assign a
during an interrupt service routine and set to
7
IMASK
is the master enable bit and must be set before any of
1
, the corresponding interrupt requests are enabled.
7
registers are
value to the master enable bit. A value change should
always be accomplished by issuing the
structions.
Care should be taken not to set or clear
while the master enable is set.
disables all the interrupt requests. Bit
Comments
Internal
External (PB4), Edge
Triggered
Internal
External (PB2), Edge
Triggered
External (PB4), Edge
Triggered
Internal
Reserved for future
expansion
EI
register individually or globally enables or dis-
and
DI
reset
instructions. It is automatically set to
to
00h
, disabling all interrupts.
Fixed Priority
1 (Highest)
2
3
4
5
6 (Lowest)
IRET
DS008700-Z8X0799
) instruction. The
0
through
EI
1
7
IMASK
following
and
is set and
ZiLOG
DI
5
bits
are
in-