m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 100

• Manufacturer Part Number: m30262f8gp
• Description: Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Three-Phase Motor Control Timer Function
94
Three-Phase Motor Control Timer Function
Figure 1.14.1. Registers related to timers for three-phase motor control (1)
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms. This function requires that P8
general purpose I/O (GPIO). If the SD feature is not needed, then P8
Three-phase PWM control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Set bit 1 of the protect register (address 000A
Note 2: Set bit 1 of this register to 1 after setting timer B2 interrupt occurrences frequency set counter.
Note 3: Effective only in three-phase mode 1(Three-phase PWM control register's bit 1 = 1 ).
Note 4: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits,
Note 5: No value other than 0 can be written.
Note 6: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the
Note 7: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger
Note 8: The value, when read, is 0 .
Note 9: The INV03 bit is set to 0 in the following cases:
Note 10: When INV03 = 1 (three-phase motor control timer output enabled) P80, P81, P72, P73, P74, and P75 function
• When reset.
• When positive and negative go active simultaneously while INV04 bit is 1 .
• When set to 0 in a program.
• When input on the SD pin changes state from H to L . (The INV03 bit cannot be set to 1 when SD input is L .)
and the timer B2 interrupt frequency set circuit works.
three-phase buffer register to the three-phase output shift register is made only once in synchronization with the
transfer trigger signal after writing to the three-phase output buffer register.
signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is
made with respect to every transfer trigger.
as U, U, V, V, W, and W.
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Bit symbol
INV00
INV01
INV02
INV03
INV04
INV05
INV06
INV07
Symbol
INVC0
Positive and negative
phases concurrent L output
disable function enable bit
Positive and negative
phases concurrent L output
detect flag
Effective interrupt output
specification bit
Mode select bit
Output control bit (Note 9)
Modulation mode select
bit
Software trigger bit
Effective interrupt output
polarity select bit
Renesas Technology Corp.
(Note 4)
Bit name
16
) to 1 before writing to this register.
Address
5
0348
become SD, making it important that P8
16
(Note 2)
(Note 4)
When reset
0: Not specified.
1: Selected by the INV00 bit.
0: Output disabled
1: Output enabled
0: Feature disabled
1: Feature enabled
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
0: Ignored
1: Trigger generated
0: A timer B2 interrupt occurs when the
1: A timer B2 interrupt occurs when the
0: Normal mode
1: Three-phase PWM output mode
0: Not detected yet
1: Already detected
00
timer A1 reload control signal is 1 .
timer A1 reload control signal is 0 .
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5
/SD must always be driven high.
Description
M16C/26 Group
(Note 10)
5
(Note 3)
(Note 3)
(Note 5)
(Note 8)
(Note 6)
(Note 7)
not be used for
R W