m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 143

• Manufacturer Part Number: m30262f8gp
• Description: Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Clock Asynchronous Serial I/O (UART) Mode
Transmission start condition
Note 1: ‘n’ denotes the value 00
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. In addition, the
Clock-Asynchronous Serial I/O Mode (used for SIM interface)
Table 1.15.12. Specifications of clock-asynchronous serial I/O mode (used for SIM interface)
Transmission/reception control
Error detection
Transfer clock
Reception start condition
Transfer data format
Other settings
Interrupt request
generation timing
The SIM (Subscriber Identity Module) interface is used for connecting the microcomputer with a memory
card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user
to use this function. Table 1.15.12 shows the specifications of clock-asynchronous serial I/O mode (used
for SIM interface).
UART2 receive interrupt request bit does not change.
Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
Item
16
to FF
• To start reception, the following requirements must be met:
• Transfer data 8-bit UART mode (bit 2, bit1, bit 0 of address 0378
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
• With the inverse format chosen
• With the internal clock chosen (bit 3 of address 0378
• Disable the CTS and RTS function (bit 4 of address 037C
• UART2 does not support sleep mode function.
• Set transmission interrupt factor to “transmission completed” (bit 4 of
• To start transmission, the following requirements must be met:
• When transmitting
• When receiving
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
(Note 1) : fi = f
- Transmit enable bit (bit 0 of address 037D
- Transmit buffer empty flag (bit 1 of address 037D
- Reception enable bit (bit 2 of address 037D
- Detection of a start bit
address 037D
Set parity to “odd” (bit 5, bit 6 of address 0378
Set data logic to “inverse” (bit 6 of address 037D
Set transfer format to MSB (bit 7 of address 037C
Set parity to “even” (bit 5, bit 6 of address 0378
Set data logic to “direct” (bit 6 of address 037D
Set transfer format to LSB (bit 7 of address 037C
- On the reception side, an “L” level is output from the TXD2 pin by use of
- On the transmission side, a parity error is detected by the level of input to
When data transmission from the UART2 transmit register is completed
When data transfer from the UART2 receive register to the UART2 receive
(bit 4 of address 037D
the parity error signal output function (bit 7 of address 037D
when a parity error is detected
16
buffer register is completed
the RXD2 pin when a transmission interrupt occurs
Renesas Technology Corp.
that is set to the UART2 bit rate generator.
1SIO
16
= “1”)
.
, f
2SIO
, f
16
8SIO
= “1”)
, f
32SIO
Specification
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Do not set external clock)
.
16
16
) = “1”
16
) = “1”
16
16
= “01
16
16
= “0”)
16
= “11
16
= “1”)
= “0”)
16
) = “0”
= “1”)
2
= “0”) : fi / 16 (n + 1)
”)
2
”)
16
M16C/26 Group
= “1”)
16
16
= “1”)
= “101
2
”)
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