ca3160t Intersil Corporation, ca3160t Datasheet - Page 5

• Manufacturer Part Number: ca3160t
• Description: 4mhz, Bimos Operational Amplifier With Mosfet Input/cmos Output
• Manufacturer: Intersil Corporation

transistor Q
provided by PMOS transistors Q
potentials for these PMOS transistors is described later. Miller
Effect compensation (roll off) is accomplished by means of the
30pF capacitor and 2k resistor connected between the base
and collector of transistor Q
provide sufficient compensation for unity gain operation in
most applications. However, additional compensation, if
desired, may be used between Terminals 1 and 8.
Bias-Source Circuit - At total supply voltages, somewhat
above 8.3V, resistor R
voltage of 8.3V across the series-connected circuit, consisting
of resistor R
A tap at the junction of resistor R
gate-bias potential of about 4.5V for PMOS transistors Q
Q
developed across diode-connected PMOS transistor Q
respect to Terminal 7 to provide gate bias for PMOS transistors
Q
both Q
be identical, the approximately 200 A current in Q
a similar current in Q
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z
across series-connected R
with variations in supply voltage. Consequently, the gate bias
for Q
voltage variations. This variation results in deterioration of the
power-supply-rejection ratio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage - The output stage consists of a drain-loaded
inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 17. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be encountered.
As a voltage follower, the amplifier can achieve 0.01% accuracy
levels, including the negative supply rail.
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000 potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.
1
5
2
becomes nonconductive and the potential, developed
with respect to Terminal 7. A potential of about 2.2V is
and Q
4
, Q
2
and Q
5
3
. It should be noted that Q
and Q
11
1
, diodes D
3
and its cascode-connected load resistance
. Since transistors Q
2
, Q
2
3
2
and Q
1
and zener diode Z
varies in accordance with supply-
through D
1
11
, D
3
as constant-current sources for
. These internal components
5
1
1
3
- D
and diode D
and Q
4
, and PMOS transistor Q
1
4
1
, Q
, and Q
is “mirror-connected” to
2
5
1
, Q
. The source of bias
serve to establish a
3
1
are designed to
, varies directly
4
provides a
1
establishes
CA3160, CA3160A
1
4
with
and
1
.
Input Current Variation with Common Mode Input
Voltage
As shown in the Electrical Specifications, the input current for
the CA3160 Series Op Amps is typically 5pA at T
when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the variation of input current as a
function of common-mode input voltage at T
data show that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate-
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CA3160 Series circuits is typically 5pA
at 25
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device, including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10
Figure 24 provides data on the typical variation of input bias
current as a function of temperature in the CA3160.
In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.
Input Offset Voltage (V
vs Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
devices in metal can packages during life testing. At lower
temperatures (metal can and plastic) for example at 85
change in voltage is considerably less. In typical linear
applications where the differential voltage is small and
symmetrical, these incremental changes are of about the same
o
C. The major portion of this input current is due to
IO
) Variation with DC Bias
o
C increase in temperature.
A
= 25
A
o
= 25
C. These
o
o
C, this
C