km416c1200c Samsung Semiconductor, Inc., km416c1200c Datasheet

km416c1200c

Manufacturer Part Number

km416c1200c

Description

1m X 16bit Cmos Dynamic Ram With Fast Page Mode

Manufacturer

Samsung Semiconductor, Inc.

Datasheet

1.KM416C1200C.pdf (34 pages)

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KM416C1000C, KM416C1200C

KM416V1000C, KM416V1200C

This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory

cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5 or -6), power con-

sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-

before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This

1Mx16 Fast Page Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power

consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

FEATURES

• Part Identification

• Active Power Dissipation

• Refresh Cycles

• Perfomance Range

Speed

C1000C

C1200C

V1000C

V1200C

- KM416C1000C/C-L (5V, 4K Ref.)

- KM416C1200C/C-L (5V, 1K Ref.)

- KM416V1000C/C-L (3.3V, 4K Ref.)

- KM416V1200C/C-L (3.3V, 1K Ref.)

-5

-6

Speed

Part

NO.

-5

-6

50ns

60ns

RAC

3.3V

324

288

15ns

CAC

3.3V

Refresh

cycle

1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

504

468

110ns

90ns

SAMSUNG ELECTRONICS CO., LTD. reserves the right to

change products and specifications without notice.

Normal

64ms

16ms

Refresh period

35ns

40ns

495

440

Unit : mW

Remark

5V/3.3V

128ms

L-ver

770

715

DESCRIPTION

(A0 - A9)

A0-A11

A0 - A7

Note)

UCAS

LCAS

RAS

: 1K Refresh

FUNCTIONAL BLOCK DIAGRAM

• Fast Page Mode operation

• 2 CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Self-refresh capability (L-ver only)

• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)

• Single +5V 10% power supply (5V product)

• Single +3.3V 0.3V power supply (3.3V product)

400mil packages

Control

Clocks

Row Address Buffer

Col. Address Buffer

Refresh Counter

Refresh Control

Refresh Timer

VBB Generator

Column Decoder

Memory Array

1,048,576 x16

Row Decoder

Cells

CMOS DRAM

Vcc

Vss

Data out

Data in

Lower

Buffer

Upper

Buffer

Upper

Buffer

DQ0

DQ7

DQ15

DQ8

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