x5323v14zt1 Intersil Corporation, x5323v14zt1 Datasheet - Page 14
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x5323v14zt1
Manufacturer Part Number
x5323v14zt1
Description
Cpu Supervisor With 32kb Spi Eeprom
Manufacturer
Intersil Corporation
Datasheet
1.X5323V14ZT1.pdf
(21 pages)
Serial Input Timing
Serial Output Timing
Notes: (3) This parameter is periodically sampled and not 100% tested.
Serial Output Timing
Symbol
t
t
f
RO
FO
t
t
SCK
SCK
(4) t
SCK
DIS
HO
t
SO
CS
SO
CS
V
(3)
(3)
SI
SI
write cycle.
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
LSB IN
ADDR
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
t
SU
High Impedance
MSB IN
14
MSB Out
t
LEAD
t
V
t
H
t
CYC
MSB–1 Out
Parameter
X5323, X5325
t
HO
t
RI
t
WH
t
WL
Min.
t
FI
0
0
LSB IN
LSB Out
2.7-5.5V
t
CS
Max.
250
250
100
100
2
t
LAG
t
t
DIS
LAG
October 27, 2005
Unit
MHz
ns
ns
ns
ns
ns
FN8131.1