lf3320 LOGIC Devices Incorporated, lf3320 Datasheet - Page 7

• Manufacturer Part Number: lf3320
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
matrix-vector multiplication, bit 4 of
Configuration Register 5 must be set
to 1 (Table 7). The configuration for
single filter mode or dual filter mode
will still apply. Writing 012H or
016H to Configuration Register 5 will
configure the device for dual filter
mode, [8x8][8x1] matrix-vector multi-
plication. Subsequently, writing 014H
to Configuration Register 5 will con-
figure the device for single filter
mode, [16x16][16x1] matrix-vector
multiplication.
Some functions of the LF3320 must
be disabled when configured for
matrix-vector multiplication. This will
apply to both the single filter mode
and the dual filter mode; these func-
tions are data reversal and interleave/
decimation. The LF3320 can be cas-
caded to realize larger matrices.
Data reversal can be disabled by set-
ting bit 6, of Configuration Register 1
(Filter A) and Configuration Register 3
(Filter B), both to 1. The Odd-Tap,
interleave mode will need to be dis-
abled. Writing a 0 to bit 0 of Con-
figuration Register 1 and Configura-
tion Register 3 will disable the odd-tap
interleave mode for Filter A and
Filter B. When data is not being inter-
F
IGURE
ROUT
8. D
SHENA / SHENB
TXFRA/ TXFRB
CENA / CENB
3-0
/COUT
DOUT
UAL
DIN
RIN
CAA
CAB
CLK
11-0
11-0
15-0
15-0
F
7-0
7-0
ILTER
*
**
***
, M
ATRIX
8 Clocks - End of First Data/Coefficient Set
10 Clocks - First Output of First Data/Coefficient Set
17 Clocks - Final Output of First Data/Coefficient Set
CF
1
Data Set 1 with 8 Coefficient Sets
00
M
DATA SET 0
CF
ULTIPLY
2
leaved or decimated, the I/D Register
length should be set to a length of one
(Table 3 and Table 5). Therefore, writ-
ing 040H to Configuration Register 1
and 3 will disable the data reversal
and set the corresponding inherent
characteristics for the desired matrix
function.
The Filter A ALU and Filter B ALU
are to be configured for A+B (Table 2
and Table 4); so that condition A+0 is
satisfied. To accomplish this, bit 0
is to be reset to 0, bit 1 is to be set
to 1, and bit 2 is to be reset to 0. Writ-
ing 002H to Configuration Register 0
(Filter A) and Configuration Register
2 (Filter B) will set the corresponding
registers to satisfy the A+0 condition.
The timing diagrams in Figure 8 and 9
will assume that the Configuration
Registers, the coefficient sets, and the
first set of data values (data set)
have been loaded. Loading input
data for an [8x8][8x1] matrix operation
requires 9 clock cycles and loading
input data for a [16x16][16x1] matrix
operation requires 17 clock cycles.
When configured for an [8x8][8x1]
matrix-vector operation, 8 data values
are required for loading. When
configured for a [16x16][16x1]
01
CF
3
02
T
IMING
S
CF
EQUENCE
8*
2-7
07
CF
9
Data Set 2 with 8 Coefficient Sets
10
DATA SET 1
CF
10**
OUT 0
11
CF
11
Horizontal Digital Image Filter
OUT 1
12
matrix-vector operation, 16 data
values are required for loading. Each
data value is fed through the I/D Reg-
isters, using the corresponding input.
Once the final data value, of the data
set, has been loaded TXFRA/TXFRB
should be brought LOW for one clock
cycle to complete the loading. Once
this occurs, the data set is then bank
loaded into the respective registers
ready to begin the matrix-vector mul-
tiplication operation. The current data
set will not change until TXFRA/
TXFRB is brought LOW again. To sat-
isfy the matrix equation (see Figure 7),
the current data set is held for
the duration of the required matrix
dimension while cycling through each
coefficient set (CENA/CENB must
be held LOW). During this time
new data values can be loaded seri-
ally, ready for the next activation of
TXFRA/TXFRB. To insure the correct
evaluation of the matrix-vector multi-
plication equation, it is imperative that
the coefficient values are paired with
their corresponding data values.
For the [8x8][8x1] matrix-vector con-
figuration (dual filter mode), the first
result will appear 19 clock cycles from
the first data input, DIN
Video Imaging Products
CF
17***
OUT 7
17
CF
18
OUT 0
20
CF
OUT 1
21
6/22/2007–LDS.3320-R
15-0
LF3320
(Filter A)