lf3320 LOGIC Devices Incorporated, lf3320 Datasheet - Page 8
lf3320
Manufacturer Part Number
lf3320
Description
Horizontal Digital Image Filter
Manufacturer
LOGIC Devices Incorporated
Datasheet
1.LF3320.pdf
(24 pages)
DEVICES INCORPORATED
and RIN
for the first result is 10 clock cycles
(10+9 = 19).
The result will appear at the cor-
responding filter output, DOUT
(Filter A) and ROUT
(Filter B). For the [16x16][16x1]
matrix-vector configuration (single
filter mode), the first result will
appear 28 clock cycles from the first
data input, DIN
for the first result is 11 clock cycles
(11+17 = 28). The result will appear
at the corresponding filter output,
DOUT
dual and single filter mode config-
urations, the sum of products will
continue to appear every clock cycle
thereafter until the matrix dimension
has been realized. The total pipeline
latency for a complete [8x8][8x1]
matrix-vector operation is 26 clock
cycles and the total pipeline latency
for a complete [16x16][16x1]
matrix-vector operation is 43 clock
cycles. Therefore, to process two
square matrices simultaneoulsy, of
size N=8, a total of 73 clock cycles
are all that is required. Similarly, to
process a single square matrix, of size
N=16, a total of 283 clock cycles are
F
IGURE
SHENA / SHENB
15-0
TXFRA/ TXFRB
CENA / CENB
15-0
9. S
. Subsequently, for both
DOUT
(Filter B); device latency
DIN
RIN
CAA
CAB
CLK
15-0
INGLE
11-0
11-0
15-0
7-0
7-0
; device latency
*
**
***
3-0
F
/COUT
ILTER
11 Clocks - First Output of First Data/Coefficient Set
16 Clocks - End of First Data/Coefficient Set
26 Clocks - Final Output From First Data/Coefficient Set
CF
, M
1
11-0
00
15-0
ATRIX
DATA SET 0
CF
2
01
M
required.
Once again, the timing diagrams (see
Figure 8 and 9) will assume that
the Configuration Registers, the coef-
ficient sets, and the data values have
been loaded. The corresponding
timing diagram loading sequence
for the coefficient banks and
Configuration/Control registers are
included in the LF3320 data sheets
(Figure 11 and Figure 12 respectively).
CF
ULTIPLY
3
F
02
IGURE
1 Data Set with 16 Coefficient Sets
T
DIN
RIN
10. D
IMING
11-0
11-0
CF
11*
OUT 0
0A
12
12
S
OUBLE
CF
2-8
EQUENCE
12
OUT 1
0B
DATA SET 0
CF
W
REGISTERS
13
DOUT
OUT 2
CIRCUIT
0C
16
FILTER
R.S.L.
IDE
I/D
A
15-0
CF
14
D
OUT 3
0D
ATA
Horizontal Digital Image Filter
CF
15
/C
0E
OUT 4
OEFFICIENT
Further reference to timing diagram
loading sequence for the RSL registers
are also included in the device data
sheet (Figure 15, Figure 14, and Figure
13). The Filter A and Filter B LF Inter-
face
Filter A and Filter B Configuration
Registers and coefficient banks.
The Matrix Multiplication Mode is
valid in the Double Wide Data/
CF
SCALE
16**
Video Imaging Products
OUT 5
0F
TM
are used to load data into the
CF
17
10
OUT 6
M
ODE
REGISTERS
FILTER
I/D
B
26***
OUT 15
6/22/2007–LDS.3320-R
LF3320