lf3321qc9 LOGIC Devices Incorporated, lf3321qc9 Datasheet - Page 12

• Manufacturer Part Number: lf3321qc9
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LF Interface ™
Continued
LOGIC Devices Incorporated
Functional Description
To load Filter A limit register 10, the first data value should be C0AH. The first address value should be
loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of LDA (see
Figures 9 and 10).
The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register
defined by the address value. When loading coefficient banks, the interface will expect eight values to be
loaded into the device after the address value. The eight values are coefficients 0 through 7. When loading
configuration or select registers, the interface will expect one value after the address value. When loading
round or limit registers, the interface will expect four values after the address value. Figures 9 and 10 show
the data loading sequences for the coefficient banks and Configuration/control registers.
Both PAUSEA and PAUSEB allow the user to effectively slow the rate of data loading through the LF
Interface
PAUSEA is returned to a LOW. When PAUSEB is HIGH, the LF Interface
B is held until PAUSEB is returned to a LOW. Figures 11 through 14 display the effects of both PAUSEA
and PAUSEB while loading coefficient and control data.
Table 15 shows an example of loading data into the coefficient banks. The following data values are written
into address 10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H.
Table 16 shows an example of loading data into a Configuration Register. Data value 003H is written into
Configuration Register 4. Table 17 shows an example of loading data into a round register. Data value
7683F4A2H is written into Filter A round register 12. Table 18 shows an example of loading data into a
select register. Data value 00FH is loaded into Filter A select register 2.
CFA/CFB
CFA/CFB
Figure 9. Coefficient Bank Loading Sequence
Figure 10. Configurational/Control Register Loading Sequence
LDA/LDB
LDA/LDB
CLK
11-0
TM
CLK
11-0
. When PAUSEA is HIGH, the LF Interface
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
ADDR
CONFIG REG
ADDR
1
DATA
1
COEFFICIENT SET 1
COEF
1
W1
ADDR
SELECT REG
0
2
DATA
1
COEF
W2
ADDR
12
7
3
ADDR
DATA
ROUND REGISTER
W1
2
1
COEFFICIENT SET 2
DATA
COEF
TM
2
0
DATA
affecting the data used for Filter A is held until
3
W3
DATA
COEF
4
Horizontal Digital Image Filter
7
ADDR
ADDR
4
W2
DATA
3
COEFFICIENT SET 3
TM
LIMIT REGISTER
COEF
1
Improved Performance
affecting the data used for Filter
DATA
0
Video Imaging Products
2
DATA
3
COEF
DATA
7
4
Feb 5, 2003 LDS.3321-A
W4
W3
LF3321