lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 11

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
one of the sixteen vertical round reg-
isters to the vertical filter output (see
Figure 11). Each round register is
32-bits wide and user-programmable.
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be pro-
grammed into the round registers, the
device can support complex rounding
algorithms as well as standard Half-
LSB rounding. VRSL
which of the sixteen vertical round
registers are used in the rounding
operation. A value of 0 on VRSL
selects vertical round register 0. A
value of 1 selects vertical round reg-
ister 1 and so on. VRSL
changed every clock cycle if desired.
This allows the rounding algorithm to
be changed every clock cycle. This is
useful when filtering interleaved data.
If rounding is not desired, a round
register should be loaded with 0 and
selected as the register used for round-
ing. Round register loading is dis-
cussed in the LF Interface
Vertical Select
The word width of the vertical filter
output is 32-bits. However, only
12-bits may be sent to the filter output.
The vertical filter select circuitry deter-
mines which 12-bits are passed (see
Table 1). The vertical select registers
control the vertical select circuitry.
There are sixteen vertical select regis-
ters. Each select register is 5-bits wide
and user-programmable. VRSL
determines which of the sixteen verti-
cal select registers are used in the ver-
tical select circuitry. A value of 0 on
11 10 9 DESCRIPTION
0 0 0 Coefficient Banks
0 0 1 Configuration Registers
0 1 0 Horizontal Select Registers
0 1 1 Vertical Select Registers
1 0 0 Horizontal Round Registers
1 0 1 Vertical Round Registers
1 1 0 Horizontal Limit Registers
1 1 1 Vertical Limit Registers
T
ABLE
8. HCF/VCF
3-0
3-0
11-9
determines
TM
may be
section.
D
ECODE
3-0
3-0
VRSL
0. A value of 1 selects vertical select
register 1 and so on. VRSL
changed every clock cycle if desired.
This allows the 12-bit window to be
changed every clock cycle. This is
useful when filtering interleaved data.
Select register loading is discussed in
the LF Interface
Vertical Limiting
An output limiting function is pro-
vided for the output of the vertical
filter. The vertical limit registers
determine the valid range of output
values when limiting is enabled (Bit
0 in Configuration Register 5). There
are sixteen 24-bit vertical limit regis-
ters. VRSL
cal limit register is used during the
limit operation. A value of 0 on
VRSL
0. A value of 1 selects vertical limit
T
T
T
REGISTER
REGISTER
REGISTER
ABLE
ABLE
ABLE
14
15
14
15
14
15
3-0
3-0
0
1
0
1
0
1
9. H
10. H
11. H
selects vertical select register
selects vertical limit register
3-0
RZ
determines which verti-
RZ
RZ
. R
TM
. S
. L
ADDRESS (HEX)
ADDRESS (HEX)
ADDRESS (HEX)
section.
11
OUND
ELECT
IMIT
Horizontal / Vertical Digital Image Filter
C0E
C0F
80E
80F
40E
40F
C00
C01
800
801
400
401
R
R
EGISTERS
3-0
EGISTERS
R
EGISTERS
may be
register 1 and so on. Each limit regis-
ter contains both an upper and lower
limit value. If the value fed to the
limiting circuitry is less than the lower
limit, the lower limit value is passed
as the filter output. If the value fed
to the limiting circuitry is greater than
the upper limit, the upper limit value
is passed as the filter output. VRSL
may be changed every clock cycle if
desired. This allows the limit range to
be changed every clock cycle. This
is useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
Interface
Coefficient Banks
The coefficient banks store the coef-
ficients which feed into the multipliers
in the horizontal and vertical filters.
T
T
T
REGISTER
REGISTER
REGISTER
ABLE
ABLE
ABLE
Video Imaging Products
14
15
14
15
14
15
0
1
0
1
0
1
12. V
13. V
14. V
TM
section.
RT
RT
RT
. R
. S
. L
ADDRESS (HEX)
ADDRESS (HEX)
ADDRESS (HEX)
IMIT
ELECT
OUND
A0E
A0F
E0E
E0F
A00
A01
600
601
60E
60F
E00
E01
R
9/14/2005-LDS.3310-I
EGISTERS
R
R
LF3310
EGISTERS
EGISTERS
3-0