ICS300 Integrated Circuit System, ICS300 Datasheet - Page 3

• Manufacturer Part Number: ICS300
• Description: Qtclock Quick Turn Clock Synthesizer
• Manufacturer: Integrated Circuit System

MDS 300QT E
Note 1: These are typical values. The actual minimum and maximum duty cycle limits are shown on the
Electrical Specifications
Parameter
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Clock Output
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz
Short Circuit Current
On-Chip Pull-up Resistor, PDTS
Input Capacitance, PDTS
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input, ICS300 and 301
Input Frequency, clock input, ICS300 and 301
Input Frequency, clock input, ICS302
Output Frequency, ICS300
Output Frequency, ICS300
Output Frequency, ICS301 and ICS302
Output Frequency, ICS301 and ICS302
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle (Note 1)
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Power-up time, PDTS goes high until Refer. out Reference on REF clk
Power-up time, PDTS goes high until CLK out
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•[phone]tel• www.icst.com
ICS300/301/302 QTClock Order Form for each programmed version.
QTClock™ Quick Turn Clock Synthesizer
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
Max of 10 seconds
ICLK (Pin 1)
ICLK (Pin 1)
PDTS
PDTS
IOH=-4mA
IOH=-25mA
IOL=25mA
CLK output
Pin 7
Pin 7
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
0.8 to 2.0V
2.0 to 0.8V
at programmed level
Deviation from mean
3
(VDD/2)+1
Minimum
VDD-0.4
-0.5
-0.5
-65
2.4
50
45
0
3
2
5
2
6
6
6
6
ICS300/ICS301/ICS302
Typical
VDD/2
VDD/2
49 to 51
±120
±70
270
20
50
4
1
1
3
8
(VDD/2)-1
Maximum
VDD+0.5
VDD+0.5
260
150
125
160
100
200
200
5.5
0.4
0.4
70
27
50
55
10
20
7
Revision 111000
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mA
mA
k
°C
°C
°C
pF
ms
ms
%
V
V
V
V
V
V
V
V
V
V
V
ns
ns
ps
ps