73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 86

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

86
t1: The time from setting VCCSEL bits until VCCOK = 1.
tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),
activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when
sequence is starting.
t2: time from start of activation (no external indication) until IO goes into reception mode (= 1).
approximately 4
t3: minimum one half of ETU period.
t4: ETU period.
Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of
CLK, either from the card or from the 73S1217F. The RST signal to the card is directly controlled by the
RSTCRD bit (non-inverted) via the MPU and is shown as an example of a possible RST pattern.
1. Clear CLKOFF after Card is in reception mode.
2. Set RST bit.
3. Interrupt is generated when Rlength counter is MAX.
4. Read and clear Interrupt.
5. Clear RST bit.
6. Toggle TX/RXB to reset bit counter.
7. Reload RLength Counter.
TX/RXB Mode bit
Rlength Interrupt
RSTCRD
IO reception on
RLength Count
VCCOK
RLenght = 1
VCCSEL
(TX = '1')
VCC
RST
CLK
bits
CLKOFF
CLKLVL
IO
Figure 23: Example of Sync Mode Operation: Generating/Reading ATR Signals
RST
CLK
SCCLK
(or SCECLK) clock cycles.
t1
tto
t1
1
2
Figure 22: Synchronous Activation
t2
Count MAX
t3
3
6
4
5
t1. CLK wll start at least 1/2 ETU after CLKOFF is set low
when CLKLVL = 0
7
t4
This is
Rev. 1.2