xr16m681 Exar Corporation, xr16m681 Datasheet - Page 15
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xr16m681
Manufacturer Part Number
xr16m681
Description
1.62v To 3.63v Uart With 32-byte Fifo And Vlio Interface
Manufacturer
Exar Corporation
Datasheet
1.XR16M681.pdf
(51 pages)
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REV. 1.0.0
F
F
IGURE
IGURE
10. R
11. R
R eceive D ata
16X or 8X or 4X C lock
Byte and Errors
32 bytes by 11-bit w ide
( D LD [5:4] )
ECEIVER
ECEIVER
16X or 8X or 4X Clock
FIFO
( DLD[5:4] )
and Errors
Data Byte
Receive
O
O
PERATION IN
PERATION IN NON
R eceive D ata Shift
R egister (R SR )
LSR bits
D ata FIFO
Tags in
FIFO
R eceive
Error
R eceive
4:2
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
D ata
-FIFO M
Receive Data Shift
AND
Register (RSR)
Holding Register
Receive Data
A
UTO
ODE
(RHR)
V alidation
D ata falls to
Trigger=16
D ata Bit
D ata fills to
FIFO
24
RTS F
E xam ple
8
15
: - R X FIFO trigger level selected at 16 bytes
LOW
R TS# re-asserts w hen data falls below the flow
control trigger level to restart rem ote transm itter.
Enable by EFR bit-6=1, M C R bit-1.
Validation
R TS# de-asserts w hen data fills above the flow
control trigger level to suspend rem ote transm itter.
Enable by EFR bit-6=1, M C R bit-1.
Data Bit
R H R Interrupt (IS R bit-2) program m ed for
(See N ote Below )
desired FIFO trigger level.
FIFO is Enabled by FC R bit-0=1
C
ONTROL
RHR Interrupt (ISR bit-2)
M
ODE
Receive Data Characters
R eceive D ata C haracters
RXFIFO1
XR16M681
R XFIFO 1