xr16m681 Exar Corporation, xr16m681 Datasheet - Page 31
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xr16m681
Manufacturer Part Number
xr16m681
Description
1.62v To 3.63v Uart With 32-byte Fifo And Vlio Interface
Manufacturer
Exar Corporation
Datasheet
1.XR16M681.pdf
(51 pages)
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REV. 1.0.0
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
•
•
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•
•
•
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM/DLD) enable.
•
•
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
LCR B
X
0
0
1
1
IT
-5 LCR B
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
X
0
1
0
1
T
ABLE
IT
-4 LCR B
10: P
0
1
1
1
1
ARITY SELECTION
IT
31
-3
Forced parity to space, LOW
Force parity to mark, HIGH
P
ARITY SELECTION
Even parity
Odd parity
No parity
XR16M681