xr16m654 Exar Corporation, xr16m654 Datasheet - Page 20

• Manufacturer Part Number: xr16m654
• Description: 1.62v To 3.63v Quad Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16M654/654D
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see
•
•
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS#
pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
The M654 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one trigger level above the selected trigger level in the trigger
table
trigger level. Under the above described conditions, the M654 will continue to accept data until the receive
FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On).
F
2.11
2.12
IGURE
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
R
(Table
X
11. R
Auto RTS (Hardware) Flow Control
Auto RTS Hysteresis
R eceive D ata
16X or 8X or 4X C lock
Byte and Errors
T
64 bytes by 11-bit w ide
RIGGER
12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected
16
56
60
8
( D LD [5:4] )
ECEIVER
L
FIFO
EVEL
O
PERATION IN
T
R eceive D ata Shift
ABLE
R egister (R SR )
INT P
D ata FIFO
FIFO
R eceive
7: A
R eceive
IN
D ata
A
16
56
60
8
UTO
CTIVATION
AND
RTS (H
A
UTO
V alidation
D ata falls to
Trigger=16
D ata fills to
D ata Bit
FIFO
56
RTS F
E xam ple
8
ARDWARE
20
: - R X FIFO trigger level selected at 16 bytes
RTS# D
(C
LOW
HARACTERS IN
R TS# re-asserts w hen data falls below the flow
control trigger level to restart rem ote transm itter.
Enable by EFR bit-6=1, M C R bit-1.
R TS# de-asserts w hen data fills above the flow
control trigger level to suspend rem ote transm itter.
Enable by EFR bit-6=1, M C R bit-1.
Figure
R H R Interrupt (IS R bit-2) program m ed for
(See N ote Below )
desired FIFO trigger level.
FIFO is Enabled by F C R bit-0=1
) F
E
C
-
LOW
ASSERTED
ONTROL
16
56
60
60
12):
C
ONTROL
R
X
M
(H
F
ODE
IFO
IGH
)
)
R eceive D ata C haracters
(C
RTS# A
HARACTERS IN
SSERTED
16
56
0
8
R X FIFO 1
R
REV. 1.0.0
(L
X
F
OW
IFO
)
)