xr16m2551im48 Exar Corporation, xr16m2551im48 Datasheet
xr16m2551im48
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE MAY 2007 GENERAL DESCRIPTION 1 The XR16M2551 (M2551 high performance dual universal asynchronous receiver and transmitter (UART) with 16 byte TX and RX FIFOs. The device operates ...
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... XR16M2551 TXRDYB# 6 48-pin TQFP TXA (Intel) Mode TXB 8 9 OP2B# CSA CSB# PWRSAVE 12 ORDERING INFORMATION ART UMBER XR16M2551IL32 32-Pin QFN XR16M2551IM48 48-Lead TQFP 1 24 RESET D6 23 RTSA INTA 3 22 RXB 21 INTB RXA TXA 19 A1 TXB ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP N T AME YPE DATA BUS INTERFACE ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE Pin Description 32-QFN 48-TQFP N T AME YPE INTB TXRDYA RXRDYA TXRDYB# - ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 Pin Description 32-QFN 48-TQFP N T AME YPE OP2A TXB RXB RTSB# ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE Pin Description 32-QFN 48-TQFP N T AME YPE 16/68 CLKSEL - 25 I RESET (RESET#) VCC ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 1.0 PRODUCT DESCRIPTION The XR16M2551 (M2551) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the XR16M2550 ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 2.3 Device Identification and Revision The XR16M2551 provides a Device Identification code and a Device Revision code to distinguish the part from other devices and revisions. To ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 2.6 DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 2.8 Crystal Oscillator or External Clock Input The M2551 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-standard data rate crystal or external clock, the divisor value can be calculated ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 2.10.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 2.11 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE IGURE ECEIVER PERATION IN 16X Clock ( DLD[5:4] ) Receive Data Shift Register (RSR) 16 bytes by 11-bit wide FIFO ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 2.13 Auto RTS Hysteresis The M2551 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the XR16C850, ST16C650A and ST16C550 family of ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 2.17 Infrared Mode The M2551 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 2.18.1 Sleep Mode All of these conditions must be satisfied for the M2551 to enter sleep mode: no interrupts pending for both channels of the M2551 (ISR ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 2.19 Internal Loopback The M2551 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to HIGH. ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M2551 has its own set of configuration registers selected by address lines A0, A1 and A2 ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit-7 0 ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals HIGH for FIFO enable; resetting IER bits 0-3 enables the XR16M2551 in the FIFO polled mode ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE MCR[3]: OP2# Output / INT Output Enable This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 LSR[3]: Receive Data Framing Error Tag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 4.12 Device Identification Register (DVID) - Read Only This register contains the device ID (0x02 for XR16M2551). Prior to reading this register, DLL and DLM should be ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD to be ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (32-QFN) ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore eliminating any unnecessary external buffers to keep the inputs steady. PAGE 21. ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE AC ELECTRICAL CHARACTERISTICS o Unless otherwise noted - YMBOL ARAMETER T Delay From Stop To Set Interrupt SSI T Delay From IOR# To Reset ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI# F 15. 16 ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE F 16 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- IGURE ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 IGURE ODE OTOROLA A0-A3 T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE F 20 & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE F 24 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0: D0:D7 (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 mm) Note: The control dimension is in millimeter. SYMBOL ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE PACKAGE DIMENSIONS (48 PIN TQFP - mm) A Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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... Updated AC Electrical Characteristics. Write data hold time values (T improved from 5ns to 3ns. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16M2551 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE GENERAL DESCRIPTION ................................................................................................ 1 A ............................................................................................................................................... 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16M2551 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE ...
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.2 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 26 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. ...