xr16v2551im Exar Corporation, xr16v2551im Datasheet - Page 29

• Manufacturer Part Number: xr16v2551im
• Description: High Performance Duart With 16-byte Fifo And Powersave Feature
• Manufacturer: Exar Corporation

REV. 1.0.2
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
must be set to ‘1’ before these bits can be accessed. Whichever selection is made last applies to both the RX
and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Whichever selection is made last applies to both the RX and TX side.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
4.6
FCR B
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
0
0
1
1
IT
Line Control Register (LCR) - Read/Write
-7
FCR B
T
0
1
0
1
ABLE
IT
-6
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
12: T
FCR B
RANSMIT AND
0
0
1
1
IT
-5
FCR
0
1
0
1
R
BIT
ECEIVE
-4
R
FIFO T
ECEIVE
1 (default)
29
L
EVEL
14
4
8
T
RIGGER
RIGGER
Table 12
T
ABLE AND
T
Table 12
RANSMIT
below shows the selections. EFR bit-4
1 (default)
L
EVEL
14
4
8
L
T
EVEL
RIGGER
shows the complete selections.
S
ELECTION
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible.
C
OMPATIBILITY
XR16V2551