xr16v2552il32 Exar Corporation, xr16v2552il32 Datasheet - Page 33

• Manufacturer Part Number: xr16v2552il32
• Description: High Performance Duart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See
RATE GENERATOR WITH FRACTIONAL DIVISOR” ON PAGE 10.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
DLD[7:6]: Reserved
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
•
•
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
AFR[7:3]: Reserved
All are initialized to logic 0.
This register contains the device ID (0x02 for XR16V2552). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
4.11
4.12
4.13
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
Alternate Function Register (AFR) - Read/Write
Device Identification Register (DVID) - Read Only
DLD[5]
0
0
1
B
IT
0
0
1
1
-2
T
ABLE
B
IT
0
1
0
1
-1
13: S
AMPLING
DLD[4]
33
X
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
0
1
Table 13
MF# F
OP2# (default)
R
BAUDOUT#
ATE
Reserved
RXRDY#
UNCTION
S
below and
ELECT
SEE”PROGRAMMABLE BAUD
S
Table 13
AMPLING
16X
8X
4X
XR16V2552
R
below.
ATE