xr16v654 Exar Corporation, xr16v654 Datasheet

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xr16v654

Manufacturer Part Number
xr16v654
Description
2.25v To 3.6v Quad Uart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet

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MAY 2007
GENERAL DESCRIPTION
The XR16V654
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, programmable transmit and receive FIFO
trigger levels, automatic hardware and software flow
control, and data rates of up to 16 Mbps at 4X
sampling rate. Each UART has a set of registers that
provide the user with operating status and control,
receiver error indications, and modem serial interface
controls.
onboard diagnostics. The V654 is available in a 48-
pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP
and 100-pin QFP packages. The 64-pin and 80-pin
packages only offer the 16 mode interface, but the
48, 68 and 100 pin packages offer an additional 68
mode interface which allows easy integration with
Motorola processors.
offers
XR16V654DIV provides continuous interrupt output.
The 100 pin package provides additional FIFO status
outputs (TXRDY# and RXRDY# A-D), separate
infrared transmit data outputs (IRTX A-D) and
channel C external clock input (CHCCLK). The
XR16V654 is compatible with the industry standard
ST16C554 and ST16C654/654D.
N
Exar
F
OTE
IGURE
:
Corporation 48720 Kato Road, Fremont CA, 94538
1 Covered by U.S. Patent #5,649,122.
RXRDY# A-D
1. XR16V654 B
TXRDY# A-D
three
CHCCLK
CLKSEL
An internal loopback capability allows
INTSEL
16/68#
A2:A0
D7:D0
IOW#
CSA#
CSB#
CSC#
CSD#
Reset
IOR#
INTD
INTC
INTB
INTA
state
1
(V654) is an enhanced quad
interrupt
LOCK
The XR16V654IV (64-pin)
Data Bus
Interface
D
IAGRAM
output
while
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
the
UART
Regs
BRG
(510) 668-7000
(same as Channel A)
(same as Channel A)
(same as Channel A)
UART Channel B
UART Channel C
UART Channel D
Crystal Osc/Buffer
* 5 Volt Tolerant Inputs
UART Channel A
(Except XTAL1 input)
FEATURES
APPLICATIONS
TX & RX
64 Byte TX FIFO
64 Byte RX FIFO
Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and Philip’s SC16C654B
Intel or Motorola Data Bus Interface select
Four independent UART channels
2.25V to 3.6V supply operation
Sleep Mode with automatic wake-up
Crystal oscillator or external clock input
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
Register Set Compatible to 16C550
Data rates of up to 16 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
ENDEC
IR
FAX (510) 668-7017
XR16V654/654D
GND
XTAL1
XTAL2
2.25V to 3.6V VCC
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
DSRD#, RTSD#, CTSD#,
CDD#, RID#
TXA, RXA, IRTXA, DTRA#,
TXB, RXB, IRTXB, DTRB#,
TXC, RXC, IRTXC, DTRC#,
TXD, RXD, IRTXD, DTRD#,
www.exar.com
654 BLK
REV. 1.0.1

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xr16v654 Summary of contents

Page 1

... XR16V654DIV provides continuous interrupt output. The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The XR16V654 is compatible with the industry standard ST16C554 and ST16C654/654D OTE 1 Covered by U.S. Patent #5,649,122. ...

Page 2

... GND 96 RXA 97 RIA# 98 CDA# 99 RXRDYA# 100 100- QFP PIN ACKAGES N AND XR16V654 100-pin QFP Intel Mode Connect 16/68# pin to VCC XR16V654 100-pin QFP Motorola Mode Connect 16/68# pin to GND 2 REV. 1.0.1 ODE 50 RXRDYC# 49 CDC# 48 RIC# 47 RXC 46 GND 45 TXRDY# 44 RXRDY# RESET 43 42 CHCCLK ...

Page 3

... DTRC# CTSB CTSC# DSRB DSRC# XR16V654 64-pin TQFP Intel Mode Only 3 XR16V654/654D 64- LQFP P ODE AND PIN ACKAGES 60 DSRD# 59 CTSD# 58 DTRD# 57 GND 56 RTSD# 55 N.C. XR16V654 54 N.C. 68-pin PLCC 53 TXD 52 N.C. Motorola Mode 51 TXC N.C. 48 RTSC# 47 VCC 46 DTRC# 45 CTSC# 44 DSRC# 48 DSRD# 47 CTSD# 46 DTRD# ...

Page 4

... PIN XR16V654 6 31 48-pin QFN XR16V654 80-pin LQFP Intel Mode only 4 REV. 1.0.1 ACKAGE RXD CTSD# GND RTSD# INTD CSD# TXD IOR# TXC CSC# INTC RTSC# N. DSRD# 58 CTSD# 57 DTRD# 56 GND ...

Page 5

... REV. 1.0.1 ORDERING INFORMATION P N ART UMBER XR16V654IJ XR16V654IV XR16V654DIV XR16V654IQ XR16V654IL XR16V654IV80 PIN DESCRIPTIONS Pin Description 48-QFN 64-LQFP 68-PLCC N AME DATA BUS INTERFACE ...

Page 6

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME IOW (R/W#) CSA (CS#) CSB (A3) CSC (A4) CSD (VCC) INTA 4 6 (IRQ#) 80-LQFP 100-QFP T YPE When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe (active low) ...

Page 7

... This pin must be LOW in the Motorola bus interface mode. For the 64 pin packages, this pin is bonded to VCC internally in the XR16V654D so the INT out- puts operate in the continuous interrupt mode. This pin is bonded to GND internally in the XR16V654 and therefore requires setting MCR bit-3 for enabling the interrupt output pins ...

Page 8

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME FSRS MODEM OR SERIAL I/O INTERFACE TXA 6 8 TXB 8 10 TXC 28 39 TXD 30 41 IRTXA - - IRTXB - - IRTXC - - IRTXD - - RXA 48 62 RXB 13 20 RXC 22 29 RXD 36 51 RTSA RTSB# ...

Page 9

... XTAL2, must be connected to this pin for normal opera- tion. This input may also be used with MIDI (Musical Instrument Digital Interface) appli- cations when an external MIDI clock is pro- vided. This pin is only available in the 100- pin QFP package. 9 XR16V654/654D D ESCRIPTION Figure 7 ...

Page 10

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME RESET 20 27 (RESET#) VCC 2, 24 35, 52 13, 47, GND 21, 47 14, 28, 6, 23, 40, 45, 61 GND Center N/A Pad N. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 80-LQFP 100-QFP ...

Page 11

... Xon/Xoff and special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps. The XR16V654 can operate from 2.25 to 3.6 volts. The V654 is fabricated with an advanced CMOS process. ...

Page 12

... UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown XR16V654 T I IGURE YPICAL NTEL ...

Page 13

... Channel A selected Channel B selected Channel C selected Channel D selected Channels A-D selected See Table A HANNEL ELECT UNCTION X X UART de-selected 0 0 Channel A selected 0 1 Channel B selected 1 0 Channel C selected 1 1 Channel D selected 13 XR16V654/654D Table 1. ODE ODE ...

Page 14

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 2.4 Channels A-D Internal Registers Each UART channel in the V654 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers ...

Page 15

... LOW = FIFO has at least 1 empty location HIGH = at least 1 byte in FIFO HIGH = FIFO is full “Section 2.8, Programmable Baud Rate Generator with Fractional R=300K to 400K 14.7456 XTAL2 XTAL1 MHz C1 C2 22-47pF 22-47pF 15 XR16V654/654D C A-D ODE FOR HANNELS ) NABLED FCR (DMA ODE NABLED ...

Page 16

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part of the divisor. Only the four lower bits of the DLD are implemented and they are used to select a value from 0 (for setting 0000 ...

Page 17

... XR16V654/654D 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX) R (%) ALUE ATE ...

Page 18

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 2.9.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1 ...

Page 19

... Data Byte and Errors 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO Figure 10 and Figure 11 below. -FIFO M ODE Receive Data Shift Data Bit Register (RSR) Validation Error Receive Data Tags in Holding Register RHR Interrupt (ISR bit-2) LSR bits (RHR) 4:2 19 XR16V654/654D Receive Data Characters RXFIFO1 ...

Page 20

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO F 11 IGURE ECEIVER PERATION IN 16X lock ( D LD [5: eceive D ata Shift R egister ( bytes by 11-bit w ide FIFO R eceive D ata Byte and Errors 2.11 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission ...

Page 21

... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 21 XR16V654/654D Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...

Page 22

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 2.14 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the V654 will halt transmission (TX) as soon as the current character has completed transmission ...

Page 23

... TO 3.6V QUAD UART WITH 64-BYTE FIFO Figure 13 below. Figure 13 NCODING AND ECEIVE ATA ECODING Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 23 XR16V654/654D 1 0 1/2 Bit Time IrEncoder IRdecoder-1 ...

Page 24

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 2.17 Sleep Mode with Auto Wake-Up The V654 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for the V654 to enter sleep mode: no interrupts pending for all four channels of the V654 (ISR bit ■ ...

Page 25

... L B IGURE NTERNAL OOP ACK IN Transmit Shift Register Receive Shift Register 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# OP2# CD# 25 XR16V654/654D TX A-D RX A-D RTS# A-D CTS# A-D DTR# A-D DSR# A-D RI# A-D CD# A-D ...

Page 26

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each UART channel in the V654 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See Table 9 and Table 10 UART CHANNEL A AND B UART INTERNAL REGISTERS ...

Page 27

... CTS# Delta Input Input Input CD# Bit-6 Bit-5 Bit-4 Bit-3 Baud Rate Generator Divisor Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Rsvd 4X Mode 8X Mode Bit-3 27 XR16V654/654D EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX Stat ...

Page 28

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS# Enable XON1 RD/WR Bit XON2 RD/WR Bit XOFF1 RD/WR Bit XOFF2 RD/WR Bit FSTAT RD RX- RDYD# 4.0 INTERNAL REGISTER DESCRIPTIONS 4 ...

Page 29

... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V654 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...

Page 30

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from LOW to HIGH (if enabled by EFR bit-6). ...

Page 31

... LSR (Receiver Line Status Register RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) 31 XR16V654/654D L EVEL S OURCE OF INTERRUPT ...

Page 32

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered) ...

Page 33

... Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO BIT-0 W ORD LENGTH 0 5 (default TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7,8 1 (default) 5 1-1/2 6,7 XR16V654/654D ...

Page 34

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • ...

Page 35

... Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth. 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO T 14: INT O M ABLE UTPUT ODES MCR INT A UTPUTS IN ODE Three-State 1 Active X Active Figure 35 XR16V654/654D 14. ...

Page 36

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an error is in the RHR ...

Page 37

... Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 37 ...

Page 38

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit divisor value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be enabled via EFR bit-4 before it can be accessed. See 2.8, Programmable Baud Rate Generator with Fractional Divisor” ...

Page 39

... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 39 XR16V654/654D ECEIVE OFTWARE LOW ONTROL ...

Page 40

... FIFO Status Register (FSTAT) - Read/Write This register is applicable only to the 100 pin QFP XR16V654. The FIFO Status Register provides a status indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the FSTAT register are placed on the data bus when the FSRS# pin (pin 76 logic 0 ...

Page 41

... Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0xFF RESET STATE HIGH LOW HIGH HIGH HIGH LOW XR16V654 = Three-State Condition (INTSEL = LOW) XR16V654 = LOW (INTSEL = HIGH) XR16V654D = LOW Three-State Condition (INTSEL = LOW) 41 XR16V654/654D ...

Page 42

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-QFN) Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) Thermal Resistance (80-LQFP) Thermal Resistance (100-QFP) ...

Page 43

... RSI 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 3.6V LOAD WHERE APPLICABLE 2.5V ± 10 XR16V654/654D L L IMITS IMITS 3.3V ± 10% U NIT MHz 50 64 MHz ...

Page 44

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay From Stop To Set Interrupt SSI T Delay From IOR# To Reset Interrupt RRI T Delay From Start To Interrupt SI T Delay From Initial INT Reset To Transmit Start ...

Page 45

... RDV Valid Data 45 XR16V654/654D Valid Address T ...

Page 46

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO F 18 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# T RDA D0- A-D US RITE IMING FOR HANNELS ...

Page 47

... T [N -FIFO M ] IMING ON ODE FOR Stop D0:D7 Bit T T SSR SSR 1 Byte 1 Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready XR16V654/654D A-D Valid Address Valid Data 68Write C A-D HANNELS D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready T RR RXNFM ...

Page 48

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO F 22 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. ...

Page 49

... SSI T SSR T [FIFO M , DMA M IMING ODE Stop Bit T D0:D7 S D0:D7 S D0: below trigger level T WRI 49 XR16V654/654D ] C A-D FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXFIFODMA A-D ODE ISABLED FOR HANNELS Last Data Byte ...

Page 50

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO F 26 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0:D7 S D0:D7 T (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into FIFO) *INT cleared when the ISR is read or when TX FIFO fills up to trigger level. ...

Page 51

... Note: The actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm. The lead may be half-etched terminal. INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.270 0.281 6.85 0.201 0.209 5.10 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.012 0.020 0.30 0.008 - 0.20 51 XR16V654/654D MAX 1.00 0.05 0.25 7.15 5.30 0.30 0.50 - ...

Page 52

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 64 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) A Seating Plane Note: The control dimension is the millimeter column SYMBOL α INCHES MILLIMETERS MIN MAX MIN 0 ...

Page 53

... BSC 1.27 BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 53 XR16V654/654D C Seating Plane 45 ° MAX 5.08 3.30 --- 0.53 0.81 0.32 25.27 24.33 23.62 1.42 1.22 1.14 ...

Page 54

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 80 LEAD PLASTIC QUAD FLAT PACK ( LQFP, 1.4 mm Form) Note: The control dimension is in the millimeter column SYMBOL α p INCHES MILLIMETERS MIN MAX MIN 0.055 0.063 1.40 0.002 0.006 0.05 0.053 0.057 1 ...

Page 55

... B e INCHES MILLIMETERS MIN MAX MIN 0.102 0.134 2.60 0.002 0.014 0.05 0.100 0.120 2.55 0.009 0.015 0.22 0.004 0.009 0.11 0.931 0.951 23.65 0.783 0.791 19.90 0.695 0.715 17.65 0.547 0.555 13.90 0.0256 BSC 0.65 BSC 0.029 0.040 0.73 0° 7° 0° 55 XR16V654/654D α L MAX 3.40 0.35 3.05 0.38 0.23 24.15 20.10 18.15 14.10 1.03 7° ...

Page 56

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO REVISION HISTORY D R ATE EVISION April 2006 Rev A1.0.0 Advanced Datasheet. May 2006 Rev P1.0.0 Preliminary Datasheet. July 2006 Rev P1.0.1 Updated AC Electrical Characteristics. October 2006 Rev P1.0.2 Updated DC Electrical Characteristics. January 2007 Rev 1.0.0 Final Datasheet. May 2007 Rev 1.0.1 Updated QFN package dimensions drawing to show minimum " ...

Page 57

... REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS F 1. XR16V654 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN UT SSIGNMENT IGURE IN UT SSIGNMENT OR PIN DESCRIPTIONS ........................................................................................................ 5 ............................................................................................................................... 5 ORDERING INFORMATION 1.0 PRODUCT DESCRIPTION .................................................................................................................... 11 2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 12 2.1 CPU INTERFACE .............................................................................................................................................. ...

Page 58

... XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 29 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 30 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 30 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ABLE RANSMIT AND ECEIVE 4 ...

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