xr16v794iv Exar Corporation, xr16v794iv Datasheet - Page 41

• Manufacturer Part Number: xr16v794iv
• Description: High Performance 2.25v To 3.6v Quad Uart With Fractional
• Manufacturer: Exar Corporation

REV. 1.0.0
Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take
advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU
bandwidth requirements.
An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO
trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger
level.
Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters
in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO
level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth
requirements.
An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0x40 (64). The RX
FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level.
These registers are used to program the Xoff1, Xoff2, Xon1 and Xon2 control characters respectively.
This register gives the status of the last sent control character (xon or xoff) and the last received control
character (xon or xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled.
XCHAR [7:4] : Reserved
XCHAR [3]: Transmit Xon Indicator
If the last transmitted control character was a xon character or characters (xon1, xon2), this bit will be set to a
logic 1. This bit will clear after the read.
XCHAR [2]: Transmit Xoff Indicator
If the last transmitted control character was a xoff character or characters (xoff1, xoff2), this bit will be set to a
logic 1. This bit will clear after the read.
XCHAR [1]: Xon Detect Indicator
If the last received control character was a xon character or characters (xon1, xon2), this bit will be set to a
logic 1. This bit will clear after the read.
XCHAR [0]: Xoff Detect Indicator
If the last received control character was a xoff character or characters (xoff1, xoff2), this bit will be set to a
logic 1. This bit will clear after the read.
4.14
4.15
4.16
4.17
4.18
4.19
TXCNT[7:0]: Transmit FIFO Level Counter - Read Only
TXTRG [7:0]: Transmit FIFO Trigger Level - Write Only
RXCNT[7:0]: Receive FIFO Level Counter - Read Only
RXTRG[7:0]: Receive FIFO Trigger Level - Write Only
XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY
XCHAR REGISTER, READ ONLY
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
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XR16V794