xr16l2550im Exar Corporation, xr16l2550im Datasheet - Page 3

• Manufacturer Part Number: xr16l2550im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

Pin Description
REV. 1.1.2
PIN DESCRIPTIONS
DATA BUS INTERFACE
RXRDYA#
TXRDYA#
IOW#
CSA#
CSB#
N
IOR#
INTB
INTA
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
AME
32-QFN
P
18
19
20
32
31
30
29
28
27
14
12
22
21
IN
2
1
7
8
-
-
#
44-PLCC
P
29
30
31
24
20
16
17
33
32
34
IN
9
8
7
6
5
4
3
2
1
#
48-TQFP
P
26
27
28
48
47
46
45
44
19
15
10
30
29
43
31
IN
11
3
2
1
#
T
YPE
IO
O
O
O
O
I
I
I
I
I
UART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. If
it is not used, leave it unconnected.
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
Input/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on
the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates
an internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address
lines.
UART channel A select (active low) to enable UART channel A in
the device for data bus operation.
UART channel B select (active low) to enable UART channel B in
the device for data bus operation.
UART channel A Interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set
to the active mode (active high) and OP2A# output to a logic 0
when MCR[3] is set to a logic 1. INTA is set to the three state
mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0
(Default).
UART channel B Interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTB is set
to the active mode and OP2B# output to a logic 0 when MCR[3] is
set to a logic 1. INTB is set to the three state mode and OP2B# to
a logic 1 when MCR[3] is set to a logic 0 (Default).
UART channel A Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channel A. If it is not
used, leave it unconnected.
3
LOW VOLTAGE DUART WITH 16-BYTE FIFO
D
ESCRIPTION
XR16L2550