xr16c854iv Exar Corporation, xr16c854iv Datasheet - Page 15

• Manufacturer Part Number: xr16c854iv
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

xr
REV. 3.0.1
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the TX FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when
the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/TX FIFO becomes empty.
The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
F
F
2.12
2.11.3
IGURE
IGURE
7. T
8. T
Receiver
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
(Xoff1/2 and Xon1/2 Reg.
Flow Control Characters
Clock
16X Clock
16X
O
O
Data
Byte
PERATION IN NON
PERATION IN
Data Byte
Transm it Shift Register (TSR)
FIFO
Transm it
-FIFO M
Register
Holding
(THR)
AND
Transm it Data Shift Register
F
LOW
ODE
RX FIFO
(TSR)
15
THR
C
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
THR Interrupt (ISR bit-1) falls
below the programm ed Trigger
Level and then when becom es
em pty. FIFO is Enabled by FCR
bit-0=1
ODE
M
S
B
TXNO FIFO 1
L
S
B
T XF IF O 1
XR16C854/854D