xr17c152im Exar Corporation, xr17c152im Datasheet
xr17c152im
Available stocks
Related parts for xr17c152im
xr17c152im Summary of contents
Page 1
JUNE 2004 GENERAL DESCRIPTION 1 The XR17C152 (152 monolithic dual PCI Bus Universal Asynchronous Receiver and Transmitter (UART) in Exar’s PCI Bus UART family. The device is designed to meet today’s 32-bit PCI Bus and high bandwidth requirement ...
Page 2
... AD26 95 AD25 96 AD24 97 C/BE3# 98 IDSEL 99 VCC 100 ORDERING INFORMATION P N ART UMBER XR17C152CM 100-Lead TQFP XR17C152IM 100-Lead TQFP XR17C152 100-TQFP (14x14x1.0mm ACKAGE PERATING EMPERATURE 0°C to +70°C -40°C to +85°C 2 áç áç áç áç REV. 1.2.0 MPIO2 ...
Page 3
REV. 1.2.0 PIN DESCRIPTIONS Pin Description AME IN YPE PCI LOCAL BUS INTERFACE RST# 86 CLK 87 AD31-AD24, 90-97, I/O AD23-AD16, 2-9, AD15-AD8, 24-31, AD7-AD0 35-42 FRAME# 13 C/BE3#-C/BE0# 98, 12, 21, ...
Page 4
XR17C152 5V PCI BUS DUAL UART Pin Description AME IN RI0# 70 TX1 62 RX1 55 RTS1# 60 CTS1# 56 DTR1# 61 DSR1# 57 CD1# 58 RI1# 59 ANCILLARY SIGNALS MPIO0-MPIO7 52-45 I/O EECK 84 EECS ...
Page 5
REV. 1.2.0 Pin Description AME IN YPE TEST# 79 VCC 10, 22, 32, 43, PWR 54, 80, 89, 100 GND 1, 11, 23, 33, PWR 44, 53, 78 63, 64 ...
Page 6
XR17C152 5V PCI BUS DUAL UART FUNCTIONAL DESCRIPTION The XR17C152 (152) integrates the functions of 2 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose ...
Page 7
REV. 1.2.0 1.0 XR17C152 REGISTERS The XR17C152 UART has three different sets of registers as shown in configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration feature makes ...
Page 8
XR17C152 5V PCI BUS DUAL UART 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS The PCI local bus configuration space registers are responsible for setting up the device’s operating environment in the PCI local bus. The pre-defined operating parameters of the ...
Page 9
REV. 1.2 PCI L ABLE DDRESS ITS YPE 0x18h 31:0 RO Unimplemented Base Address Register (returns zeros) 0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x20 31:0 RO Unimplemented Base ...
Page 10
XR17C152 5V PCI BUS DUAL UART T 2: XR17C152 D ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 - 0x0FF Reserved ...
Page 11
REV. 1.2 ABLE EVICE A DDRESS R EGISTER [A7:A0] Ox08A RESET Ox08B SLEEP Ox08C DREV Ox08D DVID Ox08E REGB Ox08F MPIOINT Ox090 MPIOLVL Ox091 MPIO3T Ox092 MPIOINV Ox093 MPIOSEL ABLE ...
Page 12
XR17C152 5V PCI BUS DUAL UART 1.2.1 The Interrupt Status Register The XR17C152 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme uses bits ...
Page 13
REV. 1.2 IGURE HE LOBAL NTERRUPT INT3 Register Rsvd Rsvd Rsvd Bit Bit Bit Bit Bit Bit Bit Bit N+2 N+1 N N+2 N+1 N N+2 N UART ...
Page 14
XR17C152 5V PCI BUS DUAL UART 1.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL XX-XX-00-00 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal crystal oscillator or ...
Page 15
REV. 1.2.0 TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these ...
Page 16
XR17C152 5V PCI BUS DUAL UART 1.2.6 SLEEP [31:24] - (default 0x00) The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. All ...
Page 17
REV. 1.2.0 REGB [23:16] (default 0x00) REGB register provides a control for simultaneous write to both UARTs configuration register or individually. This is very useful for device initialization in the power up and reset routines. Also, ...
Page 18
XR17C152 5V PCI BUS DUAL UART IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) MPIOSEL [7:0] (Select Input=1, ...
Page 19
REV. 1.2.0 MPIOLVL [7:0] (default 0x00) Output pin level control and input level status. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 ...
Page 20
XR17C152 5V PCI BUS DUAL UART 2.0 CRYSTAL OSCILLATOR / BUFFER The 152 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the 2 UARTs, the ...
Page 21
REV. 1.2.0 3.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each ...
Page 22
XR17C152 5V PCI BUS DUAL UART Channel ReceiveData in 32-bit alignment through the Configuration Register Address Receive Data Byte n PCI ...
Page 23
REV. 1.2.0 Channel Transmit Data in 32-bit alignment through the Configuration Register Address Transmit Data Byte n+3 Transmit Data Byte n ...
Page 24
XR17C152 5V PCI BUS DUAL UART 3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-BIT FORMAT The THR and RHR register address for channel 0 to channel 1 is shown in for each ...
Page 25
REV. 1.2.0 clock at 16X clock rate sampling rate, these data rates would double. When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s). ...
Page 26
XR17C152 5V PCI BUS DUAL UART F 10 IGURE RANSMITTER PERATION IN NON ...
Page 27
REV. 1.2.0 4.3 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on ...
Page 28
XR17C152 5V PCI BUS DUAL UART 4.3.3 Receiver Operation with FIFO F 13 IGURE ECEIVER PERATION IN 16X or 8X Sampling Clock (8XMODE Reg.) Receive Data Shift Register (RSR) 64 bytes by 11- bit wide FIFO Receive Data ...
Page 29
REV. 1.2.0 Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by: Setting EFR bit-4 ...
Page 30
XR17C152 5V PCI BUS DUAL UART 4.5 Infrared Mode Each UART in the 152 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates both UART channels to start ...
Page 31
REV. 1.2.0 4.6 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. ...
Page 32
XR17C152 5V PCI BUS DUAL UART Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with the EXAR enhanced feature registers located on next 8 addresses locations. Addresses 0x080 to ...
Page 33
REV. 1.2.0 T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit ...
Page 34
XR17C152 5V PCI BUS DUAL UART T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE XCHAR XOFF1 ...
Page 35
REV. 1.2.0 IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in ...
Page 36
XR17C152 5V PCI BUS DUAL UART Interrupt Generation: • LSR is by any of the LSR bits and 4. • RXRDY trigger level. • RXRDY Time-out is by the a 4-char plus 12 bits ...
Page 37
REV. 1.2.0 ISR[4]: Xoff/Xon or Special Character Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). ...
Page 38
XR17C152 5V PCI BUS DUAL UART FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for ...
Page 39
REV. 1.2.0 4.8.7 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are ...
Page 40
XR17C152 5V PCI BUS DUAL UART LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to ...
Page 41
REV. 1.2.0 MCR[5]: Xon-Any Enable Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default). Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data transmission. MCR[6]: Infrared ...
Page 42
XR17C152 5V PCI BUS DUAL UART LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In addition, this bit ...
Page 43
REV. 1.2.0 MSR[5]: DSR Input Status This input may be used for auto DTR/DSR flow control function, see CTS or DTR/DSR) Flow Control Operation” on page 28 is not used, this bit is the compliment of ...
Page 44
XR17C152 5V PCI BUS DUAL UART 4.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF ...
Page 45
REV. 1.2 ABLE ELECTABLE FCTR B -3 FCTR ...
Page 46
XR17C152 5V PCI BUS DUAL UART EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any ...
Page 47
REV. 1.2.0 EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/ DTR is selected, an interrupt will be ...
Page 48
XR17C152 5V PCI BUS DUAL UART REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-1:0] RTS#[ch-1:0] DTR#[ch-1:0] EECK EECS EEDI T 19: ...
Page 49
REV. 1.2.0 5.0 PROGRAMMING EXAMPLES 5 NLOADING ECEIVE ATA It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any UART channel (address ...
Page 50
XR17C152 5V PCI BUS DUAL UART ABSOLUTE MAXIMUM RATINGS Power Supply Range (VCC) Voltage at any pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.0mm 144-TQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA=0 ...
Page 51
REV. 1.2.0 AC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA (-40 to +85 C for industrial grade package). VCC = 4.5 - 5.5V unless otherwise specified YMBOL ARAMETER ...
Page 52
XR17C152 5V PCI BUS DUAL UART F 17. PCI B C IGURE US ONFIGURATION ost ost A D[31:0] H ost /BE [3:0]# H ost ...
Page 53
REV. 1.2 IGURE EVICE ONFIGURATION AND CLK Host FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address ...
Page 54
XR17C152 5V PCI BUS DUAL UART F 19 IGURE EVICE ONFIGURATION REGISTERS TION CLK FRAM ata AD[31: ress ...
Page 55
REV. 1.2 IGURE EVICE ONFIGURATION CLK H ost 1 FRAM E# H ost AD[31: ost Target Bus C/BE[3:0]# Byte Ena ble ...
Page 56
XR17C152 5V PCI BUS DUAL UART F 21. 5V PCI B C IGURE US LOCK 4 nSec (max) CLK Tval (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Bused Signal Input Tcyc 11 nSec 4 nSec ...
Page 57
REV. 1.2 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 23 IGURE ECEIVE ATA EADY START BIT RX Data ...
Page 58
XR17C152 5V PCI BUS DUAL UART PACKAGE DIMENSIONS 100 LEAD T HIN QUAD FLAT PACK Seating Plane YMBOL Note: The ...
Page 59
... June 2004 Rev 1.2.0 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
Page 60
XR17C152 5V PCI BUS DUAL UART REV. 1.2.0 GENERAL DESCRIPTION .................................................................................................1 A .............................................................................................................................................1 PPLICATIONS F ...................................................................................................................................................1 EATURES ..................................................................................................................................................................... 1 IGURE LOCK IAGRAM ......................................................................................................................................................... 2 IGURE THE EVICE ..............................................................................................................................2 ...
Page 61
F 10 IGURE RANSMITTER PERATION IN NON F 11 IGURE RANSMIITTER PERATION IN 4.3 R ......................................................................................................................................... 27 ECEIVER 4.3.1 Receive Holding Register (RHR) - Read-Only ......................................................................................... 27 4.3.2 Receiver Operation in non-FIFO ...
Page 62
XR17C152 5V PCI BUS DUAL UART REV. 1.2 ...................................................................................................................................59 EVISION ISTORY TABLE OF CONTENTS ................................................................................................................................. I III áç áç áç áç ...