xr21b1411 Exar Corporation, xr21b1411 Datasheet - Page 8

• Manufacturer Part Number: xr21b1411
• Description: Enhanced 1-ch Full-speed Usb Uart
• Manufacturer: Exar Corporation

XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control
described above except that it uses the DTR# and DSR# signals. GPIO3 and GPIO2 become DTR# and
DSR#, respectively, when GPIO_MODE[2:0] = ’010’ and FLOW_CONTROL[2:0] = ’001’.
When software flow control is enabled, the B1411 compares the receive data characters with the programmed
Xon or Xoff characters. If the received character matches the programmed Xoff character, the B1411 will halt
transmission as soon as the current character has completed transmission. Data transmission is resumed
when a received character matches the Xon character.
FLOW_CONTROL[2:0] = ’010’.
The B1411 device has two address matching modes which are also set by the flow mode control register using
modes 3 and 4. These modes are intended for a multi-drop network application.
XON_CHAR register holds a unicast address and the XOFF_CHAR holds a multicast address. A unicast
address is used by a transmitting master to broadcast an address to all attached slave devices that is intended
for only one slave device. A multicast address is used to broadcast an address intended for more than one
recipient device. Each attached slave device should have a unique unicast address value stored in the
XON_CHAR register, while multiple slaves may have the same multicast adderss stored in the XOFF_CHAR
register. An address match occurs when an address byte (9th bit or parity bit is ’1’) is received that matches
the value stored in either the XON_CHAR or XOFF_CHAR register.
If an address match occurs in either flow control mode 3 or 4, the address byte will not be loaded into the RX
FIFO, but all subsequent data bytes will be loaded into the RX FIFO. The UART Receiver will automatically be
disabled when an address byte is received that does not match the values in the XON_CHAR or XOFF_CHAR
register.
In flow control mode 3, the UART transmitter will transmit irrespective of the Rx address match. In flow control
mode 4, the UART will only transmit following an Rx address match.
By default, the GPIO5/RTS# pin will be de-asserted immediately after the stop bit of the last byte has been
shifted. However, this may not be ideal for systems where the signal needs to propagate over long cables.
Therefore, the de-assertion of GPIO5/RTS# pin can be delayed from 1 to 15 bit times via the
XCVR_EN_DELAY register to allow for the data to reach distant UARTs.
Half-duplex mode is enabled when FLOW_CONTROL[3] = 1. In half duplex mode, the UART will ignore any
data on the RX input when the UART is transmitting data.
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to
minimize host processing. However, in some cases where the baud rate is low this increases latency
unacceptably. The Low Latency register bit will be automatically set from CDC_ACM_IF_SET_LINE_CODING
command based whenever the baud rate is less than 40961 bps or alternately a custom driver may set the
RX_FIFO_LOW_LATENCY register bit to force RX data to be delivered without delay.
1.3.4.2
1.3.4.3
1.3.5
1.3.5.1
1.3.5.2
1.3.6
1.3.7
1.3.8
Multidrop mode with address matching
Programmable Turn-Around Delay
Half-Duplex Mode
Rx FIFO Low Latency
Automatic DTR/DSR Hardware Flow Control
Automatic XON/XOFF Software Flow Control
Receiver
Transmitter
8
Software flow control is enabled when
In these modes, the
REV. 1.1.0