xr20m1172 Exar Corporation, xr20m1172 Datasheet - Page 10

• Manufacturer Part Number: xr20m1172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 5 Mbps. To access the device in the SPI
mode, the CS# signal for the M1172 is asserted by the SPI master, then the SPI master starts toggling the SCL
signal with the appropriate transaction information. The first bit sent by the SPI master includes whether it is a
read or write transaction and the UART register being accessed. See
The 64 byte TX FIFO can be loaded with data or 64 byte RX FIFO data can be unloaded in one SPI write or
read sequence.
F
F
F
2.1.2
IGURE
IGURE
IGURE
7. SPI W
8. SPI R
9. SPI FIFO W
SPI Bus Interface
S C L K
S O
EAD
R /W A 3
RITE
A 2
RITE
SCLK
SCLK
SI
SI
B
A 1
6:3
2:1
7
0
IT
R/W A3
R/W A3
A 0 C H 1 C H 0
SO
Read/Write#
Logic 1 = Read
Logic 0 = Write
UART Internal Register Address A3:A0
UART Channel Select
’00’ = UART Channel A, other values are reserved
Reserved
A2
A2
A1
A1
X
T
ABLE
A0 CH1 CH0 X
A0 CH1 CH0 X
D 7
D 6
3: SPI F
D 5
D 4
D7
D7
D 3
IRST
10
D6
D6
D 2
F
UNCTION
D 1
D5
D5
B
YTE
D4
D4
D 0
D 7
D3
D3
F
ORMAT
D 6
D2
D2
D 5
D1
D1
Table 3
D 4
D0
D0
D 3
D 2
below.
D 1
D 0
la s t b it
REV. 1.0.0