pt7a4408 Pericom Technology Inc, pt7a4408 Datasheet - Page 7

• Manufacturer Part Number: pt7a4408
• Description: T1/e1/oc3 System Synchronizer
• Manufacturer: Pericom Technology Inc

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Functional Description
Overall Operation
The PT7A4408/4408L is a multitrunk synchronizer that pro-
vides the clock and frame signals for T1 and E1 primary rate
digital transmission links, and STS-3/OC3 links.
It basically consists of the Clock Generator, Mode Control,
Digital Phase- Locked Loop (DPLL), Analog Phase- Locked
Loop (APLL) and Output Interface Circuit.
The DPLL circuit provides synchronization of the output sig-
nals with any given input reference signal.
Master Clock
The PT7A4408/4408L uses either an external clock source or
an external crystal and a few discrete components with its
internal oscillator as the master clock.
Feedback Frequency Select MUX
The feedback frequency is selected by FS1 and FS2 (as shown
in Table 3) to match the particular incoming reference fre-
quency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must
be performed after every frequency select input change.
PT0106(09/02)
Figure 3. Block Diagram of DPLL
Reference
Frequency Select MUX
Feedback Signal
Detector
Phase
From
Limiter
Control Circuit
7
Digital Phase-Locked Loop (DPLL)
The DPLL consists of the Phase Detector, Limiter, Loop Filter,
Digitally Controlled Oscillator (DCO) and Control Circuit.
See Figure 3 for the block diagram of DPLL.
The Reference is sent to Phase Detector for comparison with
the Feedback Signal from the Feedback Frequency Select MUX.
An error signal corresponding to their instantaneous phase
difference is produced and sent to the Limiter.
The Limiter amplifies this error signal to ensure the DPLL
responds to all input transient conditions with a maximum
output phase slope of 5ns per 125 s. This performance easily
meets the maximum phase slope of 7.6ns per 125 s or 81ns per
1.326ms specified by AT&T TR62411.
The Loop Filter is a 1.9Hz low pass filter for all three reference
frequency selections: 8kHz, 1.544MHz and 2.048MHz. The
filter ensures that the jitter transfer requirements in ETS 300-
011 and AT&T TR62411 are met.
Table 3. Feedback Frequency Selection
Loop
Filter
F 2
F 2
F 2
F 2
F
S
S
S
S
S
0
0
1
1
2
T1/E1/OC3 System Synchronizer
F 1
F 1
F 1
F 1
F
S
S
S
0
0
S
S
1
1
DCO
1
PT7A4408/4408L
n I
n I
n I
n I
n I
DPLL Reference
Output Interface
p
p
p
p
p
t u
t u
t u
t u
t u
1
2
R
0 .
5 .
Circuit
e
Data Sheet
8
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r F
r F
r F
r F
4
4
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to
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4
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v r
q e
q e
q e
q e
q e
M
M
z
d e
H
H
u
u
u
u
u
n e
n e
n e
n e
n e
z
z
y c
y c
y c
y c
y c
Ver:0