73m2910l ETC-unknow, 73m2910l Datasheet - Page 14

• Manufacturer Part Number: 73m2910l
• Description: Microcontroller
• Manufacturer: ETC-unknow

Microcontroller
HDLC Control register 0 (hdlc0) sfr address 0c0H
BITS 3,2 RXD Control
Bit 3 and bit 2 control the source of the 73M2910L RXD output pin. This output goes to the DTE’s RS232
interface. The source of this signal can be the core’s UART TXD output, the PRXD output from a modem
peripheral (clear channel), the DTE’s TXD (echo), or the value written into bit 7 of this register.
BITS 1,0 PTXD Control
Bit 1 and bit 0 control the source of the 73M2910L PTXD output pin. This output goes to the modem’s TX data
input. The source of this signal can be the core’s HDLC TX output, the DTE’s TXD output (clear channel), or the
value written into bit 6 of this register.
HDLC CONTROL REGISTER 1 (HDLC1) SFR ADDRESS 0C1h
Byte Addressable
Reset State 00h
This register controls the basic set-up of the HDLC block. This register will be written during initialization and
not during normal message processing.
BIT 7 HDLC Software Reset
When bit 7 is a 1, the HDLC circuit is reset and held in a low power state and no interrupts from the HDLC
circuitry will be generated. When a 0 is written to this bit, the HDLC circuit will behave according to its control
bits.
Bit 7 and the power-on-reset signal are OR’ed together to form a reset signal for the HDLC block.
Bit 7 is cleared to a 0 upon a power-up-reset.
BIT 6 CRC Type Control
Bit 6 selects the CRC algorithm used in the 16-bit CRC calculation. There are two types of 16-bit CRCs
commonly used, CRC16 and the CCITT 16-bit CRC. If this bit is set to a 1, the CCITT type is selected.
Bit 6 is cleared to a 0 upon a reset.
HDLC
BIT 7
RST
BIT 3
BIT 1
0
0
1
1
0
0
1
1
CCITT
BIT 6
BIT 2
BIT 0
BIT 5
CRC
PRE
0
1
0
1
0
1
0
1
RXCRC
BIT 4
RXD OUTPUT
UART TXD Output
PRXD Buffered (clear channel)
TXD Buffered (echo)
WRXD (bit 7)
PTXD OUTPUT
HDLC TX Output
TXD Buffered (clear channel)
WPTXD (bit 6)
0
32
(continued)
14
RXCRC
BIT 3
16
TXCRC
CTRL
BIT 2
ZERO
BIT 1
ID
INTEN
HDLC
BIT 0