73m2910l ETC-unknow, 73m2910l Datasheet - Page 15

• Manufacturer Part Number: 73m2910l
• Description: Microcontroller
• Manufacturer: ETC-unknow

BIT 5 CRC Preset Value
Bit 5 selects the reset value for the CRC generator and receiver. If this bit is set to a 1, the CRC generator and
receiver are initialized to ones and if this bit is reset to a 0, they are initialized to 0s. This bit should be set to a 1
for most CCITT polynomials.
Bit 5 is cleared to a 0 upon a reset.
BITS 4,3 RX CRC Control
Bit 4 and bit 3 determine the type of CRC remainder that will be checked at the end of a received frame. There
is a 16-bit CRC, and a 32-bit CRC that the HDLC block can support. If both bit 4 and bit 3 are reset, bits 7 and 6
of the HDLC Status Register will be held to a 0. If both bit 4 and bit 3 are 1s, a special CRC search mode is
enabled where both bits 7 and 6 of the HDLC Status Register are enabled. This mode is used during a
connection to determine which CRC is used by the initiating modem. If the 16-bit CRC remainder is not
matched at the end of the received frame, then bit 6 of the HDLC Status Register is set. If the 32-bit CRC
remainder is not matched at the end of the received frame, then bit 7 of the HDLC Status Register is set. Once
the correct CRC type is established during a connection, either bit 4 or bit 3 should be set to a 1 enabling the
appropriate invalid CRC status bit.
BIT 2 TXCRC Control
Bit 2 controls the CRC type to be transmitted. If bit 2 is reset to a 0, a 16-bit CRC will be transmitted with the
SEND CRC command. If bit 2 is set to a 1, a 32-bit CRC will be transmitted.
BIT 1 Zero Insert/Delete Control
When bit 1 is set to a 1, a 0 will be transmitted if either the send data or send CRC bits of the HDLCTX control
are set after five consecutive 1s have been transmitted. Also, when this bit is set, a 0 will be removed from the
received data stream if it immediately follows a pattern of a 0 followed by five consecutive ones. If bit 1 is reset
to a 0, no 0s will be inserted during transmission, and no 0s will be deleted during reception.
Bit 1 is cleared to a 0 upon a reset.
BIT 0 HDLC Interrupt Enable
When bit 0 is reset to a 0, the HDLC will be prevented from generating an interrupt. The status bits that indicate
the source of the interrupt can still be set allowing the HDLC block to be serviced in a polled mode.
Bit 0 is cleared to a 0 upon reset.
BIT 4
0
0
1
1
BIT 3
0
1
0
1
CRC TYPE
NO CRC Check
Enable CRC16 Status
Enable CRC32 Status
Enable CRC16 Status and CRC32 Status
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Microcontroller