wm8973l Wolfson Microelectronics plc, wm8973l Datasheet
wm8973l
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wm8973l Summary of contents
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... Volts. Different sections of the chip can also be powered down under software control. The WM8973L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems. BLOCK DIAGRAM ...
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... WM8973L DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATION CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 OUTPUT PGA’S LINEARITY ......................................................................................... 9 HEADPHONE OUTPUT THD VERSUS POWER......................................................... 10 SPEAKER THD AND NOISE VERSUS POWER ......................................................... 11 POWER CONSUMPTION ....................................................................................12 SIGNAL TIMING REQUIREMENTS .....................................................................13 SYSTEM CLOCK TIMING............................................................................................ 13 AUDIO INTERFACE TIMING – ...
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... Production Data IMPORTANT NOTICE ..........................................................................................61 ADDRESS.................................................................................................................... 61 w WM8973L PD Rev 4.2 September 2005 3 ...
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... WM8973L PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8973LGEFL/V - +85 C WM8973LGEFL/RV - +85 C Note: Reel quantity = 3500 w PACKAGE MOISTURE SENSITIVITY LEVEL 32-lead QFN (5x5x0.9mm) MSL3 (Pb-free) 32-lead QFN (5x5x0.9mm) MSL3 (Pb-free, tape and reel) Production Data PEAK SOLDERING TEMPERATURE ...
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... Right Channel Input 3 or Headphone Plug-in Detection Left Channel Input 3 Right Channel Input 2 Left Channel Input 2 Right Channel Input 1 Left Channel Input 1 Control Interface Selection Chip Select / Device Address Selection Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input WM8973L DESCRIPTION PD Rev 4.2 September 2005 5 ...
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... WM8973L ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... Output power is very closely correlated with THD; see below. O THD HPVDD=1.8V =5mW O HPVDD=1.8V =5mW O HPVDD=3.3V =20mW O HPVDD=3.3V =20mW O SNR HPVDD = 3.3V HPVDD = 1.8V WM8973L MIN TYP MAX 1.0 0.545 22 1 -82 0.008 -74 0.02 85 0.2 AVDD/3 -84 ...
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... WM8973L Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T data unless otherwise stated. PARAMETER Speaker Output (LOUT2/ROUT2 with 8 Output Power at 1% THD Abs. Max Power Ouptut Total Harmonic Distortion Signal to Noise Ratio (A-weighted) Analogue Reference Levels Midrail Reference Voltage Buffered Reference Voltage Microphone Bias ...
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... XXXVOL Register Setting (binary XXXVOL Register Setting (binary) WM8973L LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT 100 110 120 130 LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT 100 110 120 130 PD Rev 4.2 September 2005 ...
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... WM8973L HEADPHONE OUTPUT THD VERSUS POWER 0 Headphone Pow er vs THD+N (32Ohm load) -20 -40 -60 -80 -100 Headphone Pow er vs THD+N (16Ohm load) -20 -40 -60 -80 -100 Pow er (mW Pow AVDD=1.8V AVDD=1.8V, capless AVDD=3.3V AVDD=3.3V, capless 25 30 AVDD=1.8V AVDD=1 ...
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... Production Data SPEAKER THD AND NOISE VERSUS POWER w WM8973L PD Rev 4.2 September 2005 11 ...
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... Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of the WM8973L. Operating mode: Significant power savings can be achieved by always disabling parts of the WM8973L that are not used (e.g. mic pre-amps, unused outputs, DAC, ADC, etc.) ...
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... MCLKH T MCLKY T MCLKDS o = +25 C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, A SYMBOL T MCLKL T MCLKH T MCLKY BCLK (Output) ADCLRC/ DACLRC (Outputs) ADCDAT DACDAT t DST WM8973L MIN TYP MAX UNIT 60:40 40:60 MIN TYP MAX UNIT DDA t DHT PD Rev 4.2 September 2005 ns ...
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... WM8973L Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Bit Clock Timing Information BCLK rise time (10pF load) BCLK fall time (10pF load) BCLK duty cycle (normal mode, BCLK = MCLK/n) BCLK duty cycle (USB mode, BCLK = MCLK) Audio Data Input Timing Information ...
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... C, Slave Mode 48kHz, MCLK = 256fs, 24-bit data, unless A SYMBOL t SCS t SCY t SCL t SCH t DSU t DHO t CSL t CSH t CSS CSL t t CSS SCY t t SCS SCL LSB MIN TYP MAX 80 200 Rev 4.2 September 2005 WM8973L t CSH UNIT ...
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... WM8973L CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) ...
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... On power down, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpor_dcvdd_off or AVDD drops below the minimum threshold Vpor_avdd_off. SYMBOL V pord_dcvdd V por_dcvdd_on V por_avdd_on V por_avdd_off Table 2 Typical POR Operation (typical values, not tested) w DCVDD VDD T1 Power on Reset Internal PORB Circuit GND DGND MIN TYP MAX UNIT 0.4 0.6 0.8 V 0.9 1.26 1.6 V 0.5 0.7 0.9 V 0.4 0.6 0.8 V WM8973L PD Rev 4.2 September 2005 17 ...
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... The digital filters used for recording and playback are optimised for each sampling rate used. To allow full software control over all its features, the WM8973L offers a choice wire MPU control interface fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs ...
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... LABEL DEFAULT RDCM LDCM 0 BIT LABEL DEFAULT WM8973L DESCRIPTION Left Channel Input Select 00 = LINPUT1 01 = LINPUT2 10 = LINPUT3 11 = L-R Differential (either LINPUT1- RINPUT1 or LINPUT2-RINPUT2, selected by DS) Left Channel Microphone Gain Boost 00 = Boost off (bypassed 13dB boost 10 = 20dB boost 11 = 29dB boost Right Channel Input Select ...
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... WM8973L MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono, either in the analogue domain (i.e. before the ADC the digital domain (after the ADC). MONOMIX selects the mode of operation. For analogue mono mix either the left or right channel ADC can be used, allowing the unused ADC to be powered off or used for a dc measurement conversion ...
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... RZCEN 0 5:0 RINVOL 010111 [5:0] ( 0dB ) 0 TOEN 0 WM8973L DESCRIPTION Left Volume Update 0 = Store LINVOL in intermediate latch (no gain change Update left and right channel gains (left = LINVOL, right = intermediate latch) Left Channel Input Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: LIVU must be set to un-mute. ...
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... WM8973L ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8973L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1 ...
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... HPOR 0 ADCHPD 5 HPFLREN HPFLREN ADCHPD WM8973L DEFAULT DESCRIPTION Polarity not inverted polarity invert polarity invert and R polarity invert 0 Store dc offset when high-pass filter disabled 1 = store offset 0 = clear offset 0 ADC high-pass filter enable (Digital) ...
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... WM8973L DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in 0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.5 (X-195) dB for 1 The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control register, but will not actually change the digital gain setting ...
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... Production Data AUTOMATIC LEVEL CONTROL (ALC) The WM8973L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary ...
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... WM8973L REGISTER ADDRESS R17 (11h) ALC Control 1 R18 (12h) ALC Control 2 R19 (13h) ALC Control 3 Table 13 ALC Control PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87 ...
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... When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8973L has a noise gate function that prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3 pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dB] < ...
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... Switching the 3D filter from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8973L control interface will only allow MODE3D to be changed when ADC and DAC are disabled (i.e. bits ADCL, ADCR, DACL and DACR in reg. ...
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... The WM8973L output signal paths consist of digital filters, DACs, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8973L is in ‘playback only’ or ‘record and playback’ mode. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs) ...
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... WM8973L GRAPHIC EQUALISER The WM8973L has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: Linear bass control: bass signals are amplified or attenuated by a user programmable gain ...
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... CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8973L also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will return to the original setting. This function is enabled by default ...
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... WM8973L OUTPUT MIXERS The WM8973L provides the option to mix the DAC output signal with analogue line-in signals from the LINPUT1/2/3, RINPUT1/2/3 pins or a mono differential input (LINPUT1 – RINPUT1) or (LINPUT2 – RINPUT2), selected by DS (see Table 5) . The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers) ...
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... RD2MO 0 7 RI2MO 0 6:4 RI2MOVOL 101 [2:0] (-9dB) WM8973L DESCRIPTION Left DAC to Right Mixer 0 = Disable (Mute Enable Path LMIXSEL Signal to Right Mixer 0 = Disable (Mute Enable Path LMIXSEL Signal to Right Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB Right DAC to Right Mixer ...
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... WM8973L ANALOGUE OUTPUTS LOUT1/ROUT1 OUTPUTS The LOUT1 and ROUT1 pins can drive a 16 Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting below 0101111 (minimum) mutes the output driver ...
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... DC reference for a BIT LABEL DEFAULT 8:7 OUT3SW 00 [1:0] WM8973L DESCRIPTION Similar to LOUT1VOL Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately Same as LO1VU Similar ROUT1VOL Right zero cross enable 1 = Change gain on zero cross only ...
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... WM8973L ENABLING THE OUTPUTS Each analogue output of the WM8973L can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To save power, unused outputs should remain disabled. Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop noise (see “ ...
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... Figure 11 Example Headset Detection Circuit Using Normally-Open Switch Figure 12 Example Headset Detection Circuit Using Normally-Closed Switch w BIT LABEL DEFAULT 6 HPSWEN 0 5 HPSWPOL 0 WM8973L DESCRIPTION Headphone Switch Enable 0 : Headphone switch disabled 1 : Headphone switch enabled Headphone Switch Polarity 0 : HPDETECT high = headphone 1 : HPDETECT high = speaker PD Rev 4.2 September 2005 37 ...
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... WM8973L THERMAL SHUTDOWN The speaker and headphone outputs can drive very large currents. To protect the WM8973L from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 0 150 C and the thermal shutdown circuit is enabled (TSDEN = 1 ) then the speaker and headphone amplifiers (outputs OUT1L/R, OUT2L/R and OUT3) will be disabled. ...
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... Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8973L can be configured as either a master or slave mode device master device the WM8973L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. In slave mode, the WM8973L responds with data to clocks it receives over the digital audio interface ...
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... WM8973L AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. ...
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... Figure 21 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 22 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) w WM8973L st nd (mode (mode A) PD Rev 4.2 September 2005 ...
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... WM8973L Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w Production Data PD Rev 4.2 September 2005 42 ...
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... DACLRC and BCLK to inputs ADCDAT is an output, ADCLRC, DACLRC and BCLK are inputs (slave mode) or outputs (master mode ADCDAT is tristated, ADCLRC, DACLRC and BCLK are inputs WM8973L DESCRIPTION BCLK invert bit (for master and slave modes BCLK not inverted 1 = BCLK inverted ...
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... WM8973L MASTER MODE ADCLRC AND DACLRC ENABLE In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to use e ...
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... Control Table 39 Clocking and Sample Rate Control The clocking of the WM8973L is controlled using the CLKDIV2, USB, and SR control bits. Setting the CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode. Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination of sample rates (see next page) ...
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... WM8973L MCLK MCLK ADC SAMPLE RATE CLKDIV2=0 CLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 12.288 MHz 24.576 MHz 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8 ...
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... SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8973L and the R/W bit is ‘0’, indicating a write, then the WM8973L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8973L returns to the idle condition and wait for a new start condition and valid address ...
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... POWER MANAGEMENT The WM8973L has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise important to enable or disable functions in the correct order (see Applications Information). ...
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... Power down 1 = Power up 2 MONO 0 MONOOUT Output Buffer and Mono Mixer 0 = Power down 1 = Power up 1 OUT3 0 OUT3 Output Buffer 0 = Power down 1 = Power up WM8973L DESCRIPTION divider enabled (for playback/record) divider enabled (for low-power standby) divider enabled (for fast start-up) PD Rev 4.2 September 2005 49 ...
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... WM8973L STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8973L, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA ...
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... LMIXSEL[2:0] 001010000 001010000 0 RMIXSEL[2:0] 001010000 001010000 001010000 001010000 001111001 001111001 MOUTVOL[6:0] 001111001 PD Rev 4.2 September 2005 WM8973L default page ref 21,28, 20,21,31,38 35, 37, ...
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... WM8973L DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER ADC Filter Type 0 (USB Mode, 250fs operation) ...
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... Figure 30 DAC Digital Filter Frequency Response – Type 1 Figure 31 DAC Digital Filter Ripple – Type 1 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 32 DAC Digital Filter Frequency Response – Type 2 Figure 33 DAC Digital Filter Ripple – Type 2 w 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 2 2.5 3 -0.06 0 0.05 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 0 0.05 2 2.5 3 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0. 2.5 3 WM8973L 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (Fs) 0.05 0.1 0.15 0.2 Frequency (Fs) PD Rev 4.2 September 2005 0.5 0.5 0.25 53 ...
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... WM8973L 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 34 DAC Digital Filter Frequency Response – Type 3 Figure 35 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 36 ADC Digital Filter Frequency Response – Type 0 0 -20 -40 -60 -80 -100 0 0 ...
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... Figure 41 ADC Digital Filter Ripple – Type 2 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0. 2.5 3 Figure 43 ADC Digital Filter Ripple – Type 3 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 10000 12000 14000 16000 Figure 45 De-emphasis Error (32kHz) WM8973L 0.05 0.1 0.15 0.2 Frequency (Fs) 0.05 0.1 0.15 0.2 Frequency (Fs) 2000 4000 6000 8000 10000 12000 14000 Frequency (Fs) PD Rev 4.2 September 2005 0.25 0.25 16000 55 ...
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... Figure 46 De-emphasis Frequency Response (44.1kHz -10 0 5000 10000 Frequency (Fs) Figure 48 De-emphasis Frequency Response (48kHz) HIGHPASS FILTER The WM8973L has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised by the following polynomial -10 -15 0 0.0005 0.001 Frequency (Fs) w 0.4 0.3 ...
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... Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 51 Recommended External Components Diagram w WM8973L PD Rev 4.2 September 2005 57 ...
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... It is also recommended to remove RF interference picked up on any cables using a simple first-order RC filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals with no DC bias should be fed to the WM8973L through a DC blocking capacitor, e. MICROPHONE INPUT CONFIGURATION MICROPHONE ...
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... WM8973L POWER MANAGEMENT (2) DACs Output Buffers DAL DAR LO1 RO1 LO2 RO2 ...
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... WM8973L PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed lead Half etch tie bar DETAIL 2 Dimensions (mm) Symbols MIN NOM A 0.80 0.90 0. 0.20 REF b 0.18 0.25 D 5.00 D2 3.30 3.45 5. ...
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... WM product or service unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w WM8973L PD Rev 4.2 September 2005 61 ...