tsl2580 ETC-unknow, tsl2580 Datasheet - Page 18

• Manufacturer Part Number: tsl2580
• Description: Light-to-digital Converter
• Manufacturer: ETC-unknow

TSL2580, TSL2581
LIGHT-TO-DIGITAL CONVERTER
TAOS098 − MARCH 2010
ADC Channel Data Registers (14h − 17h)
NOTE: The Read Word protocol can be used to read byte-paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as
Manual Integration Timer (18h − 19h)
18
Copyright E 2010, TAOS Inc.
TIMERHIGH
TIMERLOW
REGISTER
Address
18h 19h
The ADC channel data are expressed as 16-bit values spread across two registers. The ADC channel 0 data
registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of
channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC
value of channel 1. All channel data registers are read-only and default to 00h on power up.
The upper byte data registers can only be read following a read to the corresponding lower byte register. When
the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will read the correct value even if additional ADC
integration cycles end between the reading of the lower and upper registers.
The MANUAL INTEGRATION TIMER registers provide the number of cycles in 10.9 μs increments that
occurred during a manual start/stop integration period. The timer is expressed as a 16-bit value across two
registers. See CONTROL and TIMING Registers for further instructions in configuring a manual integration.
The maximum time that can be derived without an overflow is 714.3 ms.
the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16-bit ADC value in a single transaction
Bit :
ADDRESS
18h
19h
7
DATA0HIGH
DATA1HIGH
DATA0LOW
DATA1LOW
REGISTER
BITS
7:0
7:0
6
Table 14.
ADDRESS
Manual Integration Timer lower byte
Manual Integration Timer upper byte
Table 13. ADC Channel Data Registers
14h
15h
16h
17h
5
r
Manual Integration Timer
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BITS
7:0
7:0
7:0
7:0
4
TIMER
ADC channel 0 lower byte
ADC channel 0 upper byte
ADC channel 1 lower byte
ADC channel 1 upper byte
3
DESCRIPTION
Registers
DESCRIPTION
2
r
1
The LUMENOLOGY r Company
0
Reset
00h