ht82m9aee Holtek Semiconductor Inc., ht82m9aee Datasheet
ht82m9aee
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ht82m9aee Summary of contents
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... Internal Power-On reset (POR) Watchdog Timer (WDT) 16 I/O ports 20/24-pin SSOP (209mil) package There are two dice in the HT82M9AEE package: one is the HT82M9AE/HT82M9AA MCU, the other is a 128 8 bits EEPROM used for data memory purpose. The two dice are wrie-bonded to from HT82M9AEE. ...
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... Block Diagram Pin Assignment Rev. 1.30 HT82M9AEE 2 December 11, 2007 ...
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... USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (de- termined by software instructions) for the internal system clock. +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature............................... Total............................................................ 100mA OH 3 HT82M9AEE December 11, 2007 ...
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... OL V =3. =0. =3. Test Conditions V Conditions Without WDT prescaler Wake-up from HALT 256 WDTS+t RCSYS WDT 256 WDTS+t +t RCSYS SST OSC 4 HT82M9AEE Ta=25 C Min. Typ. Max. Unit 3.3 5 500 A 300 1.2 1 ...
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... Only relevant for repeated 4000 START condition 0 200 4000 Time in which the bus must be free before a new trans- 4700 mission can start Noise suppression time =2.2V to 5.5V 5 HT82M9AEE Ta= =5V 10% CC Unit Max. Min. Max. 100 400 kHz 600 ns 1200 ...
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... Program Counter S10 Program Counter S11~S0: Stack register bits @7~@0: PCL bits 6 HT82M9AEE * ...
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... TBLP and the current program counter bits. Table Location * Table Location P11~P8: Current program counter bits when TBHP is disabled TBHP register bit3~bit0 when TBHP is enabled 7 HT82M9AEE * December 11, 2007 ...
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... The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.30 HT82M9AEE Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... Bank 1 RAM Mapping Rev. 1.30 HT82M9AEE Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions ...
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... When the HT82M9AEE receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82M9AEE is set and a USB interrupt is also triggered. When the HT82M9AEE receives a Resume signal from Function ...
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... Host PC, the resume line (bit3 of the USC) of the HT82M9AEE are set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB in- terrupt is triggered and URST_Flag bit of the USC regis- ter is set. When the interrupt has been served, the bit should be cleared by firmware ...
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... If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. 12 HT82M9AEE (system clock SYS December 11, 2007 ...
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... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. Reset Timing Chart Rev. 1.30 HT82M9AEE The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable ...
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... HT82M9AEE USB-Reset USB-Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 00-0 1--- 00-0 1--- 000H 000H uuuu uuuu ...
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... To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set the pulse width measurement mode, the TON will be cleared au- Function TMRC (11H) Register Timer/Event Counter 15 HT82M9AEE /4 SYS /4. SYS December 11, 2007 ...
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... It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Input/Output Ports 16 HT82M9AEE December 11, 2007 ...
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... A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.30 The relationship between V ) must LVR Note the voltage range for proper chip opera- OPR tion at 6MHz or 12MHz system clock. Low Voltage Reset 17 HT82M9AEE and V is shown below. DD LVR December 11, 2007 ...
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... A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state. Byte Write Timing 18 HT82M9AEE December 11, 2007 ...
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... The EEPROM acknowl- edges the device address and serially clocks out the data word. The microcontroller should respond with a no ACK signal (high) followed by a stop condition. (refer to Random read timing). Current Read Timing Random Read Timing 19 HT82M9AEE December 11, 2007 ...
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... ACK signal (high) followed by a stop condition. Data EEPROM Timing Diagrams Note: The write cycle time t is the time from a valid stop condition of a write sequence to the end of the valid start WR condition of sequential command. Rev. 1.30 Sequential Read Timing 20 HT82M9AEE December 11, 2007 ...
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... Bit 4 Bit 3 Bit 2 Address value Default value=00000000 Bit7~Bit3 Bit 2 Bit 1 Reserved Pipe 2 Pipe 1 Pipe 2 Pipe 1 Pipe 2 Pipe 1 21 HT82M9AEE FIFO 1 FIFO 2 48H 49H 4AH Bit 1 Bit 0 Remote Wake-up Function 0: Not this function 1: The function exists Default Bit 0 Value Data 0 0000 0110 ...
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... USB Interface. The programmer must do something to save the device and keep it alive. MNI R/W This bit is for masking the NAK interrupt when MNI the default value= 0 Rev. 1.30 Read/Write MNI R/W EOT R R/W NAK OUT R/W R/W R/W SIES (45H) Registers Table Description SIES Function Table 22 HT82M9AEE Register Address 01000101B December 11, 2007 ...
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... Description MISC Function Table HT82M9AEE allows a maximum of 8 bytes of data in each packet. The HT82M9AEE FIFO is written by packet. To write to FIFO, the following should be followed: Select a set of FIFO, set in the write mode (MISC TX bit = 1), and set the REQ bit to 1 Check the ready bit until the status = 1 ...
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... ACT_PIPE as well. The timing is illustrated in the figure below. Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82M9AEE will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82M9AEE should jump to the suspend state to meet the 500 A USB sus- pend current spec ...
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... If SPS2=0, and SUSB=1, the HT82M9AEE is defined as a USB interface. Both the USBD- and USBD+ are driven by the USB SIE of the HT82M9AEE. User only writes or reads the USB data through the corresponding FIFO. Both SPS2 and SUSB default ...
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... The default value Reserved bit, set to 0 This flag is used to show that the MCU is in USB mode (Bit=1). This bit is R and will be cleared to zero after power-on USB_flag reset. The default value USR (0X1B) Register 26 HT82M9AEE December 11, 2007 ...
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... This flag is used to show that the MCU is in PS2 mode (Bit=1). This bit is R and will be cleared to zero after power-on PS2_flag reset. The default value SCC (0X1C) Register Option Functions Store current table read bit11~bit8 data TBHP (0X1F) Register Option 27 HT82M9AEE December 11, 2007 ...
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... RES to high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.30 HT82M9AEE 28 December 11, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.30 Description 29 HT82M9AEE Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.30 Description 30 HT82M9AEE Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.30 PDF PDF PDF addr PDF PDF HT82M9AEE December 11, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.30 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.30 Program Counter+1 PDF PDF PDF addr PDF PDF HT82M9AEE December 11, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.30 PDF PDF Program Counter+1 PDF PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.30 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT82M9AEE December 11, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.30 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.30 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT82M9AEE December 11, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.30 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT82M9AEE December 11, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.30 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT82M9AEE December 11, 2007 ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF HT82M9AEE December 11, 2007 ...
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... Package Information 20-pin SSOP (209mil) Outline Dimensions Symbol Rev. 1.30 Dimensions in mil Min. Nom. 291 196 9 271 65 25. HT82M9AEE Max. 323 220 15 295 December 11, 2007 ...
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... SSOP (209mil) Outline Dimensions Symbol Rev. 1.30 Dimensions in mil Min. Nom. 291 196 9 311 HT82M9AEE Max. 323 220 15 345 December 11, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 20N (209mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.30 HT82M9AEE Dimensions in mm 330 1 62 1.5 13.0+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 46 December 11, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.30 HT82M9AEE Dimensions in mm 16.0+0.3 0.1 12 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 7.1 0.1 7.2 0.1 2 0.1 0.3 0.05 13.3 47 December 11, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 HT82M9AEE 48 December 11, 2007 ...