ht82m99ee Holtek Semiconductor Inc., ht82m99ee Datasheet
ht82m99ee
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ht82m99ee Summary of contents
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... Internal Power-On reset (POR) Watchdog Timer (WDT) 12 I/O ports 20-pin DIP/SOP package There are two dice in the HT82M99EE/HT82M99AE package: one is the HT82M99EE/HT82M99AE MCU, the other is a 128 8 bits EEPROM used for data mem- ory purpose. The two dice are wire-bonded to form HT82M99EE/HT82M99AE. ...
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... Block Diagram Pin Assignment Rev. 1.30 HT82M99EE/HT82M99AE 2 August 13, 2007 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.30 HT82M99EE/HT82M99AE Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register) ...
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... System Start-up Timer Period SST t Crystal Setup OSC Note: Power-on period WDT SST OSC WDT Time-out in normal mode=1/f WDT Time-out in HALT mode=1/f Rev. 1.30 HT82M99EE/HT82M99AE Test Conditions V Conditions load, f =6MHz SYS 5V No load, system HALT, USB suspend load, system HALT, input/output mode, 5V set SUSPEND2 [1CH] ...
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... SCL Pins) t Write Cycle Time WR Note: These parameters are periodically sampled but not 100% tested * The standard mode means V CC For relative timing, refer to timing diagrams Rev. 1.30 HT82M99EE/HT82M99AE Standard Mode* Remark Min. 4000 4700 Note Note After this period the first ...
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... Return from Subroutine S10 Note: *10~*0: Program counter bits #10~#0: Instruction code bits Rev. 1.30 HT82M99EE/HT82M99AE After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. ...
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... TABRDL [ Note: *10~*0: Table location bits @7~@0: TBLP bits Rev. 1.30 HT82M99EE/HT82M99AE ROM data by two table read instructions: TABRDC and TABRDL , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows: ...
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... Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through memory pointer registers (MP0 or MP1). Rev. 1.30 HT82M99EE/HT82M99AE Bank 0 RAM Mapping 8 August 13, 2007 ...
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... Bank 1 RAM Mapping Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.30 HT82M99EE/HT82M99AE Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... USB interrupt request flag (1=active; 0=inactive Internal timer/event counter request flag (1:active; 0:inactive) Rev. 1.30 HT82M99EE/HT82M99AE Function Status (0AH) Register rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the SP is decremented ...
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... The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82M99EE/ HT82M99AE, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can eas- ily decide which FIFO is accessed ...
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... Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following: The system oscillator will be turned off but the WDT Rev. 1.30 HT82M99EE/HT82M99AE Watchdog Timer oscillator remains running (if the WDT oscillator is se- lected). The contents of the on-chip RAM and registers remain unchanged ...
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... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. Reset Timing Chart Rev. 1.30 HT82M99EE/HT82M99AE The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable ...
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... USR 0100 0000 uuuu uuuu SCC 0000 0000 uuuu uuuu Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.30 HT82M99EE/HT82M99AE RES Reset WDT RES Reset (Normal Time-Out (HALT) Operation) (HALT)* 0000 0000 0000 0000 uuuu uuuu ...
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... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.30 HT82M99EE/HT82M99AE nal (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the f (Timer). The pulse width measurement mode can be used to count the high or low level duration of the exter- nal signal (TMR) ...
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... CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high/low resistor struc- tures can be reconfigured dynamically under software Rev. 1.30 HT82M99EE/HT82M99AE control. To function as an input, the corresponding latch of the control register must write The input source also depends on the control register. If the control regis- ter bit the input will read the pad state ...
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... Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.30 HT82M99EE/HT82M99AE The relationship between V ) must LVR ...
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... EEPROM sends a zero to acknowledge that it has re- ceived each word. This happens during the ninth clock cycle. Rev. 1.30 HT82M99EE/HT82M99AE Device Addressing The 1K EEPROM devices all require an 8-bit device ad- dress word following a start condition to enable the chip for a read or write operation. The device address word ...
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... The address roll over during write from the Rev. 1.30 HT82M99EE/HT82M99AE last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and ac- knowledged by the EEPROM, the current address data word is serially clocked out ...
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... The bitmaps are listed as follows: Register Register Name R/W Address Pipe_ctrl R/W 01000001B STALL R/W 01000011B PIPE R 01000100B STALL (43H) and PIPE (44H) Registers Rev. 1.30 HT82M99EE/HT82M99AE STALL PIPE SIES MISC 43H 44H 45H Bank 1, Address 40H, 4AH, 4FH Register Memory Mapping Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Address value ...
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... End of transient flag, normal status suspend= 1 line & EOT= 0 indicates that EOT R something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. MNI R/W This bit is for masking the NAK interrupt when MNI the default value= 0 Rev. 1.30 HT82M99EE/HT82M99AE Read/Write MNI R/W EOT R R/W NAK R ...
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... FIFO pointer register (FIFO0, FIFO1). The following are two examples for reading and writing the FIFO data: HT82M99EE/HT82M99AE FIFO is read by packet. To read from FIFO, the following should be followed: Select one set of FIFO, set in the read mode (MISC TX bit = 0), and set the REQ bit ...
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... The user can also further decrease the suspend current to 250 A by setting the SUSP2 (bit4 of the SCC). But if the SUSP2 is set, the user has to make sure not to en- able the LVR OPT option, otherwise the HT82M99EE/ HT82M99AE will be reset. When the resume signal is sent out by the host, the HT82M99EE/HT82M99AE will wake-up the MCU by Rev ...
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... RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from the HT82M99EE/HT82M99AE, it will send a Resume signal to the device. The timing is as follows: To Configure the HT82M99EE/HT82M99AE as PS2 Device The HT82M99EE/HT82M99AE can be defined as a USB interface or a PS2 interface by configuring the I/O Port Special Registers Definition Port-A (12H) PA Bit No. ...
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... PEC4 R/W 5 PEC5 R/W 7 PEC7 R/W Rev. 1.30 HT82M99EE/HT82M99AE Option Functions USB suspend mode status bit. When 1, indicates that the USB SUSPEND system entry is in suspend mode. RMOT_WK USB remote wake-up signal. The default value When RESUME_OUT EVENT, RESUME_O is set RESUME_O The default value ...
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... TBHP enable/disable (default: disable output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Note: The LVR voltage is define as 2.7V 0.3V and default is enable. Rev. 1.30 HT82M99EE/HT82M99AE Option Functions Reserved USB clock control bit. When set indicates a USBCK ON, USBCKEN else USBCK OFF. The default value ...
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... RES to high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.30 HT82M99EE/HT82M99AE 27 August 13, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.30 HT82M99EE/HT82M99AE Description 28 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.30 HT82M99EE/HT82M99AE Description 29 Instruction Flag Cycle Affected 2 ...
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... ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF PDF PDF ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF PDF addr PDF OV Z ...
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... Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF PDF OV ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE Program Counter+1 PDF PDF PDF ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF Program Counter+1 ...
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... Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE Stack PDF Stack PDF ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF OV Z ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF PDF ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF PDF ...
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... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.30 HT82M99EE/HT82M99AE PDF PDF PDF OV ...
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... Package Information 20-pin DIP (300mil) Outline Dimensions Symbol Rev. 1.30 HT82M99EE/HT82M99AE Dimensions in mil Min. Nom. 1020 240 125 125 16 50 100 295 335 0 43 Max. 1045 260 135 145 20 70 315 375 15 August 13, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.30 HT82M99EE/HT82M99AE Dimensions in mil Min. Nom. 394 290 14 490 Max. 419 300 20 510 104 August 13, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 20W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.30 HT82M99EE/HT82M99AE Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 45 August 13, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.30 HT82M99EE/HT82M99AE Dimensions in mm 24+0.3 0.1 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 46 August 13, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 HT82M99EE/HT82M99AE 47 August 13, 2007 ...