ht82m9bee Holtek Semiconductor Inc., ht82m9bee Datasheet
ht82m9bee
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ht82m9bee Summary of contents
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... Internal Power-On reset (POR) Watchdog Timer (WDT) 20 I/O ports 28-pin SOP (300mil) package There are two dice in the HT82M9BEE package: one is the HT82M9BE/HT82M9BA MCU, the other is a 128 8 bits EEPROM used for data memory purpose. The two dice are wrie-bonded to from HT82M9BEE. ...
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... Block Diagram Pin Assignment Rev. 1.30 HT82M9BEE 2 December 11, 2007 ...
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... USBD- or PS2 DATA I/O line USB or PS2 function is controlled by software control register OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (de- termined by software instructions) for the internal system clock. +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature............................... Total............................................................ 100mA OH 3 HT82M9BEE December 11, 2007 ...
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... V =0. =3. =0. =3. Test Conditions V Conditions Without WDT prescaler Wake-up from HALT 256 WDTS+t RCSYS WDT 256 WDTS+t +t RCSYS SST OSC 4 HT82M9BEE Ta=25 C Min. Typ. Max. Unit 3.3 5 250 A 230 1.2 1.4 V 2.0 5 0.9V ...
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... Only relevant for repeated 4000 START condition 0 200 4000 Time in which the bus must be free before a new trans- 4700 mission can start Noise suppression time =2.2V to 5.5V 5 HT82M9BEE Ta= =5V 10% CC Unit Max. Min. Max. 100 400 kHz 600 ns 1200 ...
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... Program Counter+2 *11 * #11 # Program Counter S12~S0: Stack register bits @7~@0: PCL bits 6 HT82M9BEE * ...
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... TABRDC [m] reads the ROM Table Location * Table Location P12~P8: Current program counter bits when TBHP is disabled TBHP register bit4~bit0 when TBHP is enabled 7 HT82M9BEE * December 11, 2007 ...
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... The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.30 HT82M9BEE Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions. The ALU provides the following functions: Rev. 1.30 HT82M9BEE Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ ...
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... When the HT82M9BEE receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82M9BEE is set and a USB interrupt is also triggered. When the HT82M9BEE receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82M9BEE are set and a USB interrupt is triggered ...
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... OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. The HT82M9BEE can operate in 6MHz or 12MHz sys- tem clocks. In order to make sure that the USB SIE func- tions properly, user should correctly configure the SCLKSEL bit of the SCC Register ...
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... Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the re- set conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets . 12 HT82M9BEE (system clock SYS December 11, 2007 ...
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... HT82M9BEE USB Reset USB Reset (Normal) (HALT) 000H 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 ...
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... TMR0 location; writing TMR0 makes the starting value be placed in the Timer/Event Counter 0 preload register and reading TMR0 gets the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. 14 HT82M9BEE USB Reset USB Reset (Normal) (HALT) 00-0 1--- 00-0 1--- ...
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... Timer/Event Counter 0/1. But if the Timer/Event Counter 0/1 is turned on, data written to it will only be kept in the Timer/Event Counter 0/1 preload register. The Timer/Event Counter 0/1 will still Function TMR0C (0EH) Register Function TMR1C (11H) Register 15 HT82M9BEE December 11, 2007 ...
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... PCC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high/low resistor struc- tures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write The input source Input/Output Ports 16 HT82M9BEE December 11, 2007 ...
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... The LVR uses the OR function with the external RES signal to perform a chip reset. The relationship between V Note the voltage range for proper chip opera- OPR tion at 6MHz or 12MHz system clock. Low Voltage Reset 17 HT82M9BEE ) must LVR and V is shown below. DD LVR December 11, 2007 ...
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... If the device is still busy imple- menting its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. Byte Write Timing 18 HT82M9BEE December 11, 2007 ...
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... The sequential read operation is terminated when the microcontroller responds with a no ACK sig- nal (high) followed by a stop condition. Current Read Timing Random Read Timing Sequential Read Timing 19 HT82M9BEE December 11, 2007 ...
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... Endpoint (Bit=0). Rev. 1.30 SIES MISC Endpt_EN FIFO0 45H 46H 47H 48H Register Memory Mapping Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Address value Default value=00000000 20 HT82M9BEE FIFO1 FIFO2 FIFO3 49H 4AH 4BH Bit 0 Remote Wake-up Function 0: Not this function 1: The function exists December 11, 2007 ...
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... Pipe 3 Pipe 2 Pipe 1 Pipe 3 Pipe 2 Pipe 1 Pipe 3 Pipe 2 Pipe 1 Read/Write MNI R/W EOT R R/W NAK OUT R/W R/W R/W SIES (45H) Registers Table Description SIES Function Table 21 HT82M9BEE Default Bit 0 Value Data 0 0000 1110 Pipe 0 0000 1110 Pipe 0 0000 1111 Register Address 01000101B December 11, 2007 ...
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... Description MISC Function Table The HT82M9BEE allows a maximum of 8 bytes of data in each packet. The HT82M9BEE FIFO is written by packet. To write to FIFO, the following should be followed: Select a set of FIFO, set in the write mode (MISC TX bit = 1), and set the REQ bit to 1 Check the ready bit until the status = 1 ...
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... ACT_PIPE as well. The timing is illustrated in the figure below. Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82M9BEE will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82M9BEE should jump to the suspend state to meet the 500 A USB sus- pend current spec ...
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... USC). Once the USB Host receive the wake-up signal from the HT82M9BEE, it will send a Resume signal to the device. The timing is as follows: To Configure the HT82M9BEE as PS2 Device The HT82M9BEE can be defined as a USB interface or a PS2 interface by configuring the SPS2 (bit 4 of the USR) and SUSB (bit 5 of the USR) ...
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... The default value Reserved bit, set to 0 This flag is used to show that the MCU is in USB mode (Bit=1). USB_flag This bit is R and will be cleared to zero after power-on reset. The default value USR (0X1B) Register 25 HT82M9BEE December 11, 2007 ...
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... This flag is used to show that the MCU is in PS2 mode (Bit=1). This bit is R and will be cleared to zero after power-on PS2_flag reset. The default value SCC (0X1C) Register Option Functions Store current table read bit12~bit8 data TBHP (0X1F) Register Option 26 HT82M9BEE December 11, 2007 ...
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... RES high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.30 HT82M9BEE 27 December 11, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.30 Description 28 HT82M9BEE Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.30 Description 29 HT82M9BEE Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.30 PDF PDF PDF addr PDF PDF HT82M9BEE December 11, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.30 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.30 Program Counter+1 PDF PDF PDF addr PDF PDF HT82M9BEE December 11, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.30 PDF PDF Program Counter+1 PDF PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.30 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT82M9BEE December 11, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.30 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.30 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT82M9BEE December 11, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.30 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT82M9BEE December 11, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.30 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT82M9BEE December 11, 2007 ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.30 PDF PDF PDF PDF HT82M9BEE December 11, 2007 ...
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... Package Information 28-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.30 Dimensions in mil Min. Nom. 394 290 14 697 HT82M9BEE Max. 419 300 20 713 104 December 11, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.30 HT82M9BEE Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 44 December 11, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.30 HT82M9BEE Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 45 December 11, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 HT82M9BEE 46 December 11, 2007 ...