ht82k72e Holtek Semiconductor Inc., ht82k72e Datasheet
ht82k72e
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ht82k72e Summary of contents
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... I/O control product applications. With its inter- nal 27MHz amplifier the device is suitable for applica- tions such as 27MHz or 2.4GHz keypads etc. Block Diagram Rev. 1.00 HT82K72E/HT82K72A 36 I/O bi-directional lines with pull-high options Supports max keyboard applications Power down and wake-up functions to reduce power consumption ...
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... I Crystal or RC OSC2 O Rev. 1.00 HT82K72E/HT82K72A Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options de- termine if the pins have pull-high resistors. PA2 is shared with the external timer input pin TMR ...
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... PC6 Internal Pull-high Resis- R PH1 tance Other Pins Internal Pull-high Re- R PH2 sistance Rev. 1.00 HT82K72E/HT82K72A Description Negative power supply, ground Schmitt trigger reset input. Active low Positive power supply AMP GND Internal Modulated RF Output AMP power supply +6.0V Storage Temperature ............................ 125 ...
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... OST t Low Voltage Detector Voltage LVD t Low Voltage Width to Reset LVR f Timer I/P Frequency (TMR) TIMER t Crystal Setup OSCsetup Power AMP A.C. Characteristics Parameter Amp. Power Amp. Load Impedance Rev. 1.00 HT82K72E/HT82K72A Test Conditions Min. V Conditions WDTS=1 1 200 Test Conditions Min. V Conditions ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. System Clocking and Pipelining Instruction Fetching 5 HT82K72E/HT82K72A February 20, 2008 ...
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... PCL bits #10~#0: Instruction code address bits S10~S0: Stack register bits Rev. 1.00 HT82K72E/HT82K72A Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited ...
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... After a device reset is initiated, the program will jump to this location and begin execu- tion. Rev. 1.00 HT82K72E/HT82K72A Location 008H This vector is used by the timer/event counter counter overflow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full ...
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... TBHP register bit2~bit0 when TBHP is enabled @7~@0: Table Pointer TBLP bits Rev. 1.00 HT82K72E/HT82K72A This will ensure that the first data read from the data ta- ble will be at the Program Memory address 706H or 6 locations after the start of the last page. Note that the ...
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... Data Memory. Rev. 1.00 HT82K72E/HT82K72A Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and ...
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... However, it must be noted that when the Mem- ory Pointer is read, bit 7 will be read as high. ; setup size of block ; setup memory pointer with first RAM address ; clear the data at address defined increment memory pointer ; check if last memory location has been cleared 10 HT82K72E/HT82K72A February 20, 2008 ...
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... Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Rev. 1.00 HT82K72E/HT82K72A Otherwise, the ROM code option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as de- fined by TBLP and the current program counter bits. ...
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... With each I/O port there is an associated control register labeled PAC, Rev. 1.00 HT82K72E/HT82K72A PBC, PCC, PDC and PE4~7 (control I/O PE0~3), also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs ...
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... However, it should be noted that the pro- gram will in fact only read the status of the output data latch and not the actual logic status of the output pin. Rev. 1.00 HT82K72E/HT82K72A Input/Output Ports Pin-shared Functions The flexibility of the microcontroller range is greatly en- hanced by the use of pins that have more than one func- tion ...
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... One of these is a high to low transition of any of the selected wake-up pins. 16-bit Timer/Event Counter Structure Rev. 1.00 HT82K72E/HT82K72A Timer/Event Counters The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. The device contains an inter- nal 16-bit count-up timer which has three operating modes ...
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... At the same time the data in the low byte buffer Timer/Event Counter Control Register Rev. 1.00 HT82K72E/HT82K72A will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It ...
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... PA2/TMR pin and stop counting when the PA2/TMR pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop Timer Mode Timing Chart Event Counter Mode Timing Chart 16 HT82K72E/HT82K72A February 20, 2008 ...
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... In this mode when the appropriate timer Rev. 1.00 HT82K72E/HT82K72A register is full, the microcontroller will generate an inter- nal interrupt signal directing the program flow to the re- spective internal interrupt vector. For the pulse width ...
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... The Program Counter will then be loaded with a new address which will be the value of the correspond- Rev. 1.00 HT82K72E/HT82K72A ing interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruc- tion at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine ...
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... By disabling the interrupt enable bit, the requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this Rev. 1.00 HT82K72E/HT82K72A condition in the interrupt control register until the corre- sponding interrupt is serviced or until the request flag is cleared by a software instruction. ...
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... RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be Rev. 1.00 HT82K72E/HT82K72A inhibited. After the RES line reaches a certain voltage value, the reset delay time t is invoked to provide ...
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... SST WDT Time-out Reset during Power Down Timing Chart Rev. 1.00 HT82K72E/HT82K72A Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer ...
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... Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. 22 HT82K72E/HT82K72A RES Reset WDT Time-out (HALT) (HALT)* 000H ...
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... If the configuration options have enabled the Watchdog Timer internal oscillator then this will continue to run when in the Power Down Mode and will thus consume Rev. 1.00 HT82K72E/HT82K72A some power. For power sensitive applications it may be therefore preferable to use the system clock source for the Watchdog Timer. ...
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... Watchdog Timer time-out completely dependent upon the fre- quency the internal WDT oscillator. Rev. 1.00 HT82K72E/HT82K72A Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. How- ever, if the system is in the Power Down Mode, when a ...
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... R/W Name 0~7 Period Timer R/W Rev. 1.00 HT82K72E/HT82K72A Internal Register - PG Description The time interval, one seconds as a unit. When <7:0>=0H then the Hardware motion detector will only wake-up the MCU when it detects mouse movement or when there is a button change for the mouse mode. For the I/O mode, MCU will only be woken Port I INT when < ...
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... PA, PB, PC, PD, PE0~PE1 falling edge wake-up by nibble: None-wake-up or wake-up 3 PA0~PA7 pull-high by bit none-pull-high or pull-high 4 PC, PD, PB, PE0~PE3 Pull-high by nibble None-Pull high or Pull high 5 LVR disable or enable 6 Power Amp. gain full or half 7 Output slew enable 100ns or 200ns TBHP function enable or disable Rev. 1.00 HT82K72E/HT82K72A Slew Rate 100ns 200ns Options 26 February 20, 2008 ...
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... Application Circuits Rev. 1.00 HT82K72E/HT82K72A 27 February 20, 2008 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT82K72E/HT82K72A subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.00 HT82K72E/HT82K72A Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 HT82K72E/HT82K72A Description 30 Cycles Flag Affected ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 HT82K72E/HT82K72A 31 February 20, 2008 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 HT82K72E/HT82K72A addr 32 February 20, 2008 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82K72E/HT82K72A February 20, 2008 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 HT82K72E/HT82K72A addr 34 February 20, 2008 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 35 HT82K72E/HT82K72A February 20, 2008 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 36 HT82K72E/HT82K72A February 20, 2008 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT82K72E/HT82K72A February 20, 2008 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT82K72E/HT82K72A February 20, 2008 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 HT82K72E/HT82K72A [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 39 February 20, 2008 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 HT82K72E/HT82K72A 40 February 20, 2008 ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 395 291 8 613 HT82K72E/HT82K72A Max. 420 299 12 637 February 20, 2008 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 HT82K72E/HT82K72A Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 42 February 20, 2008 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 HT82K72E/HT82K72A Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 43 February 20, 2008 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT82K72E/HT82K72A 44 February 20, 2008 ...