ht82k75rew Holtek Semiconductor Inc., ht82k75rew Datasheet - Page 56

• Manufacturer Part Number: ht82k75rew
• Description: Ht82m75rew/ht82k75rew 2.4ghz Transceiver 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Rev. 1.00
SCLK, clock frequency
SCLK low pulse duration
SCLK high pulse duration
SEN setup time
SEN hold time
SI setup
SI hold time
Rise time
Fall time
SPI Addressing Format
MSB of addressing frame indicates the addressing mode of the packet. The length of address field is 6 or 10 bits for
short and long addressing mode respectively. Bit 0 is a one-bit read/write indicator.
SPI Characteristics
SPI Timing Diagram
The following figures show the timing diagrams for the short and long addressing mode respectively. The MCU SPI
master will initiate a read or write operation by asserting the interface enable signal SEN to low, toggling SCLK and
sent the address field by SI. The interface enable signal SEN should be high when a transaction is completed.
Parameter
SCLK
SEN
SO
SO
SI
SI
t
read short address data
SP
write short address data
0
0
A6 A5
A6 A5
Symbol
f
t
t
SCLK
RISE
FALL
t
t
t
t
t
t
CH
SP
NS
SD
HD
CL
t
SD
A4
A4
Timing Diagram of Short Addressing Mode
A3
A3
A2 A1 0
A2 A1 1
Min.
100
100
100
100
25
25
t
HD
SPI Addressing Format
D
D
R
Max.
w
7 D
7
25
25
D
5
R
w
6
6
D
D
R
w
5
5
t
D
D
56
CH
R
w
MHz
4
Unit
4
ns
ns
ns
ns
ns
ns
ns
ns
D
D
R
w
X
3 D
3 D
R
w
2
2
D
D
The minimum time SCLK must be low.
The minimum time SCLK must be high.
The minimum time SEN must be low before the first
positive edge of SCLK.
The minimum time SEN must be held low after the
last negative edge of SCLK.
The minimum time data must be ready at SI, before
the positive edge of SCLK
The minimum time data must be held at SI, after the
positive edge of SCLK.
The maximum rise time for SCLK and SEN.
The maximum fall time for SCLK and SEN.
R
w
t
1
1
CL
D
D
R
w
0
0
HT82M75REW/HT82K75REW
0 A6
0
A6 A5
A5 A4 A3 A2 A1 0
A4
A3
A2 A1 1
Conditions
D
D
R
w
7
7
D
D
X
R
w
6
6 D
D
t
w
R
5
5
NS
June 11, 2010