ht82k96e Holtek Semiconductor Inc., ht82k96e Datasheet
ht82k96e
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ht82k96e Summary of contents
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... This device is an 8-bit high performance RISC-like microcontroller designed for USB product applications particularly suitable for use in products such as Rev. 2.00 HT82K96E 4 endpoints supported (endpoint 0 included) 4096 15 program memory ROM 160 8 data memory RAM HALT function and wake-up feature reduce power ...
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... Block Diagram Rev. 2.00 2 HT82K96E October 11, 2007 ...
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... PB6, PB7 can be used as USB mouse button input for mouse Hardware wake-up function Bidirectional I/O lines. Software instructions determine the CMOS out- put or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high option). PD4 can be used as USB mouse button input for mouse hardware wake-up function 3 HT82K96E October 11, 2007 ...
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... SYS f =12MHz SYS 5V No load, f =6MHz SYS 5V No load, f =12MHz SYS No load, system HALT, 5V USB suspend No load, system HALT, 5V USB suspend =3. =0. =0. HT82K96E Ta=25 C Min. Typ. Max. Unit 4.4 5.5 V 4.4 5 250 A 230 0.4V 0 ...
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... Test Conditions Min. Typ. Max. V Conditions Without WDT prescaler 4 8 Without WDT prescaler 1024 1 Wake-up from HALT 1024 Power-up, Watchdog 1024 Time-out from normal HT82K96E Max. Unit 4 LSB Ta=25 C Unit 12 MHz 12 MHz 70 s ...
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... Program Counter S10 Program Counter S11~S0: Stack register bits @7~@0: PCL bits 6 HT82K96E * ...
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... The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. Table Location * Table Location P11~P8: Current program counter bits 7 HT82K96E * October 11, 2007 ...
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... All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through memory pointer registers (MP0 or MP1). 8 HT82K96E October 11, 2007 ...
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... Any data written into the status register will not change the TO or PDF flag. In addi- tion operations related to the status register may give different results from those intended. Function Status (0AH) Register 9 HT82K96E October 11, 2007 ...
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... Host PC, the suspend line (bit0 of USC) of the HT82K96E is set and a USB interrupt is also triggered. Also when HT82K96E receive a Resume signal from Host PC, the resume line (bit3 of USC) of HT82K96E is set and a USB interrupt is triggered. Whatever there are USB reset signal is detected, the USB interrupt is triggered ...
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... This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Watchdog Timer 11 HT82K96E October 11, 2007 ...
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... To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur: RES reset during normal operation RES reset during HALT WDT time-out reset during normal operation 12 HT82K96E (system clock SYS October 11, 2007 ...
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... The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear Clear. After master reset, WDT WDT begins counting Timer/event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack 13 HT82K96E October 11, 2007 ...
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... HT82K96E USB-Reset USB-Reset (Normal) (HALT) uuuu uuuu uuuu uuuu 00-0 1000 00-0 1000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...
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... Rev. 2.00 The Timer/Event Counter 1 contains an 16-bit program- mable count-up counter and the clock may come from an external source or from the system clock divided by 4. Function TMR0C (0EH) Register Function TMR1C (11H) Register Timer/Event Counter 0 Timer/Event Counter 1 15 HT82K96E October 11, 2007 ...
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... SYS TMR0/TMR1) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the program- mer. 16 HT82K96E October 11, 2007 ...
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... It should be noted that a non-pull-high/low I/O line operating in input mode will cause a floating state recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Input/Output Ports 17 HT82K96E October 11, 2007 ...
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... HT82K96E will wake-up the MCU by I/O method, otherwise the MCU is in suspend mode. How long the HT82K96E to turn on the IRPT, and the low pulse period of the PC0 is defined by bit0~3 of the WDTS (wake-up period) and the bit0~bit2 of the SCC (LED_on period) respectively. The following diagram show the IRPT control pin timing ...
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... PS2DAO should set to 1. Otherwise it always read 0. If SPS2=0, and SUSB=1, the HT82K96E is defined as USB interface. Both the USBD- and USBD+ is driving by SIE of the HT82K96E. The user only write or read the USB data through the corresponding FIFO. Both SPS2 and SUSB is default 0 . ...
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... Stall the endpoint 3 7~4 W Unused bit, read as 0 Bit No. Label R/W 0 EP0RW R Endpoint 0 accessed 1 EP1RW R Endpoint 1 accessed 2 EP2RW R Endpoint 2 accessed 3 EP3RW R Endpoint 3 accessed 7~4 R Unused bit, read as 0 Rev. 2.00 Function AWR (42H) Register Function STALL (43H) Register Function PIPE (44H) Register 20 HT82K96E October 11, 2007 ...
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... It is used to indicate that a 0-sized packet is sent from host to MCU. This bit should be 7 LEN0 R/W cleared by firmware. Rev. 2.00 Bit5 Bit4 Bit3 Bit2 Reserved bit 01000101B Description SIES (45H) Register Table Function MISC (46H) Register 21 HT82K96E Bit1 Bit0 F0_ERR Adr_set R/W R/W October 11, 2007 ...
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... Function USC (1AH) Register 22 HT82K96E Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0 Data7~Data0 ...
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... WDT timer overflow will wake-up MCU system 1 : WDT timer overflow will start hardware wake-up detect circuit but not wake-up MCU system. Rev. 2.00 Function USR (1BH) Register Function 001: 3 base 011: 9 base 101: 33 base 111: 127 base SCC (1CH) Register 23 HT82K96E October 11, 2007 ...
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... WDT enable or disable 9 WDT clock source WDTOSC SYS 10 CLRWDT instruction(s PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain (by bit) 12 PA0~PA7 wake-up enabled or disabled (by bit) 13 A/D converter enabled or disabled Rev. 2.00 Function ADSC (1DH) Register Function ADR (1EH) Register Option 24 HT82K96E October 11, 2007 ...
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... RES to high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 2.00 25 HT82K96E October 11, 2007 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 26 HT82K96E October 11, 2007 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 27 HT82K96E Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 2.00 Description 28 HT82K96E Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 2.00 29 HT82K96E October 11, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 2.00 addr 30 HT82K96E October 11, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 2. HT82K96E October 11, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 2.00 addr 32 HT82K96E October 11, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 2.00 Stack Stack Stack [m]. 0~6) 33 HT82K96E October 11, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 2.00 [m]. 0~6) 34 HT82K96E October 11, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 2.00 [ HT82K96E October 11, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 2.00 0 [m] [ HT82K96E October 11, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 2.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 37 HT82K96E October 11, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 2.00 38 HT82K96E October 11, 2007 ...
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... Package Information 28-pin SOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 394 290 14 697 HT82K96E Max. 419 300 20 713 104 October 11, 2007 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 395 291 8 613 HT82K96E Max. 420 299 12 637 October 11, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 41 HT82K96E October 11, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 42 HT82K96E October 11, 2007 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 43 HT82K96E October 11, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.00 44 HT82K96E October 11, 2007 ...