ht82k95ee Holtek Semiconductor Inc., ht82k95ee Datasheet
ht82k95ee
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ht82k95ee Summary of contents
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... All instructions in one or two machine cycles 28-pin SOP package There are two dice in the HT82K95EE/HT82K95AE package: one is the HT82K95E/HT82K95A MCU, the other is a 128 8 bits EEPROM used for data memory purpose. The two dice are wire-bonded to form HT82K95EE/HT82K95AE ...
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... Block Diagram Pin Assignment Rev. 1.20 HT82K95EE/HT82K95AE 2 August 28, 2006 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.20 HT82K95EE/HT82K95AE Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register) ...
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... Watchdog Time-out Period (WDT OSC) WDT1 t Watchdog Time-out Period (System Clock) WDT2 t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 1.20 HT82K95EE/HT82K95AE Test Conditions Min. Typ. V Conditions DD f =6MHz 4.2 SYS f =12MHz 4.2 SYS 5V No load, f =6MHz 6 ...
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... SCL Pins) t Write Cycle Time WR Note: These parameters are periodically sampled but not 100% tested * The standard mode means V CC For relative timing, refer to timing diagrams Rev. 1.20 HT82K95EE/HT82K95AE Standard Mode* Remark Min. 4000 4700 Note Note After this period the first 4000 ...
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... Return from subroutine S11 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.20 HT82K95EE/HT82K95AE incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call or return ...
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... Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.20 HT82K95EE/HT82K95AE Location 00CH This location is reserved for the Timer/Event Counter 1 interrupt service program timer interrupt results from a Timer/Event Counter 1 overflow, and the inter- rupt is enabled and the stack is not full, the program begins execution at location 00CH ...
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... MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table higher-order Rev. 1.20 HT82K95EE/HT82K95AE Bank 0 RAM Mapping (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA ...
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... set by a WDT time-out. 6~7 Unused bit, read as 0 Rev. 1.20 HT82K95EE/HT82K95AE Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator ...
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... The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82K95EE/ HT82K95AE, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can eas- ily decide which FIFO is accessed ...
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... This oscillator is designed for system clocks. The HALT mode stops the system oscillator and ignores an exter- nal signal to conserve power. Rev. 1.20 HT82K95EE/HT82K95AE A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of ...
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... The PDF flag is cleared by a system power-up or exe- cuting the CLR WDT instruction and is set when exe- Rev. 1.20 HT82K95EE/HT82K95AE cuting the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only 1:1 ...
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... PC 1111 1111 1111 1111 PCC 1111 1111 1111 1111 PD 1111 1111 1111 1111 Rev. 1.20 HT82K95EE/HT82K95AE Reset Configuration The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear Clear. After master reset, WDT WDT begins counting ...
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... To enable/disable timer 1 counting (0=disabled; 1=enabled) To define the operating mode 01=Event count mode (external clock) 6 TM0 10=Timer mode (internal clock) 7 TM1 11=Pulse width measurement mode 00=Unused Rev. 1.20 HT82K95EE/HT82K95AE RES Reset WDT RES Reset (Normal Time-Out (HALT) Operation) (HALT)* 1111 1111 1111 1111 ...
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... The TMR1C is the Timer/Event Counter 1 control register, which defines the operating mode, counting en- able or disable and active edge. Rev. 1.20 HT82K95EE/HT82K95AE Timer/Event Counter 0 Timer/Event Counter 1 The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0/TMR1) pin ...
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... PCC, PDC) to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt trigger input with or without pull-high resistor Rev. 1.20 HT82K95EE/HT82K95AE structures can be reconfigured dynamically under soft- ware control. To function as an input, the corresponding latch of the control register must write The input source also depends on the control register ...
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... Since low voltage has to be maintained for over 1ms in its original state, therefore there s a 1ms delay before entering the reset mode Rev. 1.20 HT82K95EE/HT82K95AE The relationship between the voltage range for proper chip opera- ...
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... EEPROM sends a zero to acknowledge that it has re- ceived each word. This happens during the ninth clock cycle. Rev. 1.20 HT82K95EE/HT82K95AE Device Addressing The 1K EEPROM devices all require an 8-bit device ad- dress word following a start condition to enable the chip for a read or write operation. The device address word ...
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... The address roll over during read from the last byte of the last memory page to the first byte of the Rev. 1.20 HT82K95EE/HT82K95AE first page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the ...
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... HT82K95EE/HT82K95AE The device with remote wake up function can wake up the USB Host by sending a wake-up pulse through RMWK (bit 1 of the USC). Once the USB Host receives a wake-up signal from the HT82K95EE/HT82K95AE, it will send a Resume signal to the device. The timing is as follows: 20 ...
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... If SPS2=0, and SUSB=1, the HT82K95EE/HT82K95AE is configured as a USB interface. Both the USBD- and USBD+ is driven by the SIE of the HT82K95EE/ HT82K95AE. User can only write or read the USB data through the corre- sponding FIFO. Both SPS2 and SUSB default ...
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... This bit is used to control whether the USB interrupt is output to the MCU in NAK re- sponse to the PC Host IN or OUT token. 1: has only USB interrupt, data is transmitted to the PC host or data is received from NMI R/W the PC Host 0: always has USB interrupt if the USB accesses FIFO0 Default 0 Rev. 1.20 HT82K95EE/HT82K95AE Bit5 Bit4 Bit3 Bit2 CRC_ERR NAK IN OUT ...
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... Check whether FIFO0 can be read or not Check whether FIFO1 can be written or not Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence to FIFO1 Note: *: There are 2 s existing between 2 reading action or between 2 writing action Rev. 1.20 HT82K95EE/HT82K95AE Function MISC (46H) Register Bank Address 1 48H ...
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... R/W The USB function is selected when this bit is set (Default This flag is used to show the MCU is in USB mode. (Bit=1) 7 USB_flag R/W This bit is R and will be cleared to 0 after power-on reset. (Default Rev. 1.20 HT82K95EE/HT82K95AE Function USC (1AH) Register Function USR (1BH) Register 24 August 28, 2006 ...
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... PA0~PA7 wake-up enabled or disabled (by bit) 12 PB0~PB7 wake-up enabled or disabled (by nibble) 13 PC0~PC7 wake-up enabled or disabled (by nibble) 14 PD0~PD7 wake-up enabled or disabled (by nibble) 15 TBHP enable or disable (default disable) Rev. 1.20 HT82K95EE/HT82K95AE Function SCC (1CH) Register Read/Write Option R/W Store current table read bit11~bit8 data Option 25 Functions ...
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... RES high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible. Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.20 HT82K95EE/HT82K95AE 26 August 28, 2006 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.20 HT82K95EE/HT82K95AE Description 27 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.20 HT82K95EE/HT82K95AE Description 28 Instruction Flag Cycle Affected 2 ...
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... ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF PDF PDF ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF PDF addr PDF OV Z ...
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... Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF PDF OV ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Program Counter ¬addr Operation Affected flag(s) TO ¾ MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. ACC ¬ [m] Operation Affected flag(s) TO ¾ Rev. 1.20 HT82K95EE/HT82K95AE PDF ¾ ¾ ¾ 1 PDF ¾ ¾ ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF Program Counter+1 ...
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... Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE Stack PDF Stack PDF ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF OV Z ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF PDF ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF PDF ...
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... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.20 HT82K95EE/HT82K95AE PDF PDF PDF OV ...
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... Package Information 28-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.20 HT82K95EE/HT82K95AE Dimensions in mil Min. Nom. 394 290 14 697 Max. 419 300 20 713 104 August 28, 2006 ...
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... Product Tape and Reel Specifications Reel Dimensions SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.20 HT82K95EE/HT82K95AE Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 43 August 28, 2006 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.20 HT82K95EE/HT82K95AE Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 44 August 28, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or sys- tems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT82K95EE/HT82K95AE 45 August 28, 2006 ...