ht82j30r Holtek Semiconductor Inc., ht82j30r Datasheet - Page 22

• Manufacturer Part Number: ht82j30r
• Description: Ht82j30r/ht82j30a -- 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

able other interrupts. Note that any pull-high resistor
configuration options on these pins will remain valid
even if the pins are used as external interrupt inputs.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ETI, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter interrupt request flag, TF, is set, a
situation that will occur when the Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter overflow occurs, a
subroutine call to the timer interrupt vector at location
08H, will take place. When the interrupt is serviced, the
timer interrupt request flag, TF, will be automatically re-
set and the EMI bit will be automatically cleared to dis-
able other interrupts.
SPI Interrupt
For an SPI Interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding SPI interrupt enable bit,
ESII_A or ESII_B, must be first set. The SBEN bit in the
SBCR register must also be set. An actual SPI Interrupt
will take place when one of the two SPI interrupt request
flags, SIF_A or SIF_B, is set, a situation that will occur
when 8-bits of data are transferred or received from ei-
ther of the SPI interfaces. When the interrupt is enabled,
the stack is not full and an SPI_A interrupt occurs, a sub-
routine call to the SPI_A interrupt vector at location 10H,
will take place. For an SPI_B interrupt, a subroutine call
to the SPI_B interrupt vector at location 14H, will take
place. When the interrupt is serviced, the SPI interrupt
request flag, SIF_A or SIF_B, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
Rev. 1.10
Interrupt Structure
22
A/D Interrupt
For an A/D converter interrupt to occur, the global inter-
rupt enable bit, EMI, and the corresponding A/D con-
verter interrupt enable flag, EADI, must first be set. An
actual A/D Interrupt will take place when the A/D con-
verter interrupt request flag, ADF, is set, as situation that
will occur when the A/D Converter conversion process
has completed. When the interrupt is enabled, the stack
is not full and an A/D conversion process has com-
pleted, a subroutine call to location 0CH will take place.
When the interrupt is serviced, the A/D interrupt request
flag, ADF, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corre-
sponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the CALL
subroutine instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a CALL subroutine is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the accumulator or status register are al-
tered by the interrupt service program, which may cor-
rupt the desired control sequence, then the contents
should be saved in advance.
HT82J30R/HT82J30A
March 13, 2008