ht82j31a Holtek Semiconductor Inc., ht82j31a Datasheet - Page 15

• Manufacturer Part Number: ht82j31a
• Description: 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

will be in an unknown condition. Note that if the
Timer/Event Counter is not running and data is written to
its preload register, this data will be immediately written
into the actual counter. However, if the counter is en-
abled and counting, any new data written into the
preload register during this period will remain in the
preload register and will only be written into the actual
counter the next time an overflow occurs.
Timer Control Register - TMRC
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of the Timer Control Register TMRC. To-
gether with the TMR register, these two registers control
the full operation of the Timer/Event Counter. Before the
timer can be used, it is essential that the TMRC register
is fully programmed with the right data to ensure its cor-
rect operation, a process that is normally carried out
during program initialisation.
To choose which of the three modes the timer is to oper-
ate in, the timer mode, the event counting mode or the
pulse width measurement mode, bits TM0 and TM1
must be set to the required logic levels. The timer-on bit
TON or bit 4 of the TMRC register provides the basic
Rev. 1.00
Timer/Event Counter Control Register
Timer Mode Timing Chart
15
on/off control of the timer, setting the bit high allows the
counter to run, clearing the bit stops the counter. Bits
0~2 of the TMRC register determine the division ratio of
the input clock prescaler. The prescaler bit setting has
no effect if an external clock source is used. If the timer
is in the event count or pulse width measurement mode
the active transition edge level type is selected by the
logic level of the TE or bit 3 of the TMRC register.
Configuring the Timer Mode
In this mode, the timer can be utilised to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, bits
TM1 and TM0 of the TMRC register must be set to 1 and
0 respectively. In this mode, the internal clock is used as
the timer clock. The input clock frequency to the timer is
f
prescaler, the value of which is determined by bits
PSC0~PSC2 of the TMRC register. The timer-on bit,
TON, must be set high to enable the timer to run. Each
time an internal clock high to low transition occurs, the
timer increments by one. When the timer is full and over-
flows, the timer will be reset to the value already loaded
into the preload register and continue counting. If the
timer interrupt is enabled, an interrupt signal will also be
SYS
divided by the value programmed into the timer
September 19, 2007
HT82J31A