ht82b40r Holtek Semiconductor Inc., ht82b40r Datasheet
ht82b40r
Available stocks
Related parts for ht82b40r
ht82b40r Summary of contents
Page 1
... USB 2.0 low speed function 3 endpoints supported - endpoint 0 included 4096 15 program memory 160 8 data memory RAM General Description The HT82B40R and HT82B40A are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, ...
Page 2
... Block Diagram Pin Assignment Rev. 1.10 HT82B40R/HT82B40A 2 September 4, 2009 ...
Page 3
... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 HT82B40R/HT82B40A Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions deter- mine if the pin is a CMOS output or NMOS, PMOS or Schmitt Trigger input ...
Page 4
... OH3 PA1~PA7,PC,PD and PE0~PE1 Pull-high Resistance for CLK, DATA R Pull-high Resistance for PB PH Pull-high Resistance for PA, PC, PD and PE0~PE1 Note: * include 15k loading on the USBD+, USBD- lines at the host terminal. Rev. 1.10 HT82B40R/HT82B40A Test Conditions Min. V Conditions DD f =6MHz or 12MHz 3.3 SYS No load, f ...
Page 5
... WDT Time_out in Power Down Mode = 1/ f Trimmed for 5V operation using factory trim values. Frequency Trim to 12MHz 3% Rev. 1.10 Test Conditions V Conditions DD 5V 4.0V~ 10.80 5.5V 3.0~ 10.56 4.0V 4.2~ 11.82 5. OSCsetup 256 WDTS + t RCSYS WDT 256 WDTS + t RCSYS OST 5 HT82B40R/HT82B40A Ta=25 C Min. Typ. Max. Unit 32 kHz 1/f 1024 RCSYS 75 300 ns t 1024 SYS 5 ms 12.00 13.20 MHz 12.00 13.44 MHz 12.00 12.18 MHz ...
Page 6
... JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. System Clocking and Pipelining Instruction Fetching 6 HT82B40R/HT82B40A September 4, 2009 ...
Page 7
... Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits Rev. 1.10 HT82B40R/HT82B40A If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced ...
Page 8
... SIZA, SDZA, CALL, RET, RETI Program Memory The Program Memory is the location where the user code or program is stored. The HT82B40R is a One-Time Pro- grammable, OTP, memory type device where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer ...
Page 9
... Table Read - TBLP only Rev. 1.10 HT82B40R/HT82B40A After setting up the table pointers, the table data can be retrieved from the current Program Memory page or last Program Memory page using the TABRDC[m] or TABRDL [m] instructions, respectively. When these in- ...
Page 10
... All are implemented in RAM and are 8 bits wide. The start address of the Data Memory for all devices is the address 00H . Registers which are com- Rev. 1.10 HT82B40R/HT82B40A mon to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory ...
Page 11
... Pointer MP1. Bank 1 can only be accessed indirectly us- ing the MP1 Memory Pointer, direct addressing is not possible. Special Purpose Data Memory Rev. 1.10 HT82B40R/HT82B40A Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc ...
Page 12
... Their values can be changed, for example using the INC or DEC instructions, allowing for easy table Rev. 1.10 HT82B40R/HT82B40A data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. ...
Page 13
... This bit is cleared when an in- terrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Rev. 1.10 HT82B40R/HT82B40A Status Register Timer/Event Counter Registers - TMR0, TMR0C, TMR1H, TMR1L, TMR1C Both devices possess a single internal 8-bit count-up timer ...
Page 14
... PMOS transistors. A pin or nibble option on the I/O ports can be selected to select pull-high Resistors. Rev. 1.10 HT82B40R/HT82B40A Port A CMOS/NMOS/PMOS Structure The pins on Port A can be setup via configuration option to be either CMOS, NMOS or PMOS types. Port B VDD/V33O Option Structure The power supply for the Port B pins can be setup via configuration option to be either VDD or V33O ...
Page 15
... I/O pins. Rev. 1.10 HT82B40R/HT82B40A Programming Considerations Within the user program, one of the first things to con- sider is port initialisation. After a reset, all of the data and port control register will be set high ...
Page 16
... Rev. 1.10 HT82B40R/HT82B40A curs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated ...
Page 17
... Timer/Event Counter 0 Structure 16-bit Timer/Event Counter 1 Structure Timer/Event Counter 0 Control Register Timer/Event Counter 1 Control Register Rev. 1.10 HT82B40R/HT82B40A 17 September 4, 2009 ...
Page 18
... The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode, the second is to ensure that Timer Mode Timing Chart Event Counter Mode Timing Chart 18 HT82B40R/HT82B40A Bit7 Bit6 0 1 September 4, 2009 ...
Page 19
... Pulse Width Measure Mode Timing Chart Rev. 1.10 HT82B40R/HT82B40A pin and stop counting when the external timer pin re- turns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting ...
Page 20
... Rev. 1.10 HT82B40R/HT82B40A associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application ...
Page 21
... The microcontroller will then fetch its next instruction from Rev. 1.10 HT82B40R/HT82B40A this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt ser- vice routine ...
Page 22
... In cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always Rev. 1.10 HT82B40R/HT82B40A INTC Register Interrupt Structure have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences ...
Page 23
... The most important reset condition is after Rev. 1.10 HT82B40R/HT82B40A power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, af- ter a short delay, will well defined state and ready to execute the first program instruction ...
Page 24
... PA7 used as a reset pin, the correct reset configuration option must be se- lected. RES Reset Timing Chart Rev. 1.10 HT82B40R/HT82B40A Low Voltage Reset LVR The microcontroller contains a low voltage reset cir- cuit in order to monitor the supply voltage of the de- vice ...
Page 25
... PC 1111 1111 1111 1111 PCC 1111 1111 1111 1111 Rev. 1.10 HT82B40R/HT82B40A The following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts ...
Page 26
... The clock source for these devices is provided by an in- tegrated oscillator requiring no external components. This oscillator has two fixed frequencies of either 6MHz, or 12MHz, the selection of which is made by the SYSCLK bit in the SCC register. Rev. 1.10 HT82B40R/HT82B40A RES Reset WDT RES Reset (Normal Time-out ...
Page 27
... Timer internal oscillator then this will continue to run when in the Power Down Mode and will thus consume Rev. 1.10 HT82B40R/HT82B40A some power. For power sensitive applications it may be therefore preferable to use the system clock source for the Watchdog Timer. If any I/O pins are configured as ...
Page 28
... WDTS7 at MCU reset) Bit7=0, USB reset signal cannot reset MCU Rev. 1.10 HT82B40R/HT82B40A Once the internal WDT oscillator (RC oscillator normally with a period selected first divided by 256 (8-stages) to get the nominal time-out period of approxi- mately 20ms. This time-out period may vary with tem- perature, VDD and process variations ...
Page 29
... If SPS2=0, and SUSB=1, the device is configured as a USB interface. Both the USBD- and USBD+ is driven by the SIE of the HT82B40R/ HT82B40A . The user can only write or read the USB data through the correspond- ing FIFO. Both the SPS2 and SUSB default ...
Page 30
... Non-USB mode, V33O output 3.3V, both D+and D- can be read and write This flag is used to indicate that the MCU is in the USB mode - Bit=1 USB_flag 7 R/W This bit is R and will be cleared to 0 after power-on reset - Default= 0 Rev. 1.10 HT82B40R/HT82B40A Function USC (20H) Register Function USR (21H) Register 30 September 4, 2009 ...
Page 31
... SE0 4 SE1 5~7 Rev. 1.10 Function SCC (22H) Register Bit7~Bit3 Bit 2 Bit 1 Reserved Pipe 2 Pipe 1 Pipe 2 Pipe 1 Pipe 2 Pipe 1 Pipe 2 Pipe 1 Read/Write R/W R/W R/W R/W R/W USB_STAT (40H) Register Table 31 HT82B40R/HT82B40A Default Bit 0 Value DATA0 00000111 Pipe 0 00000111 Pipe 0 00000000 Pipe 0 00000111 Register Address 01000000B September 4, 2009 ...
Page 32
... PC Host IN or OUT token. Only for Endpoint0 1: has only USB interrupt, data is transmitted to the PC host or data is received from the PC NMI R/W Host 0: always has USB interrupt if the USB accesses FIFO0 Default 0 Rev. 1.10 HT82B40R/HT82B40A Description USB_STAT Function Table Read/Write R/W R/W R/W SIES (45H) Register Table ...
Page 33
... Check whether FIFO0 can be read or not Check whether FIFO1 can be written or not Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence to FIFO1 Note: *: There time between 2 read actions or between 2 write actions. Rev. 1.10 HT82B40R/HT82B40A Function MISC (46H) Register Bank Address 1 48H ...
Page 34
... PA0~7 wake-up by bit, (default enable) 10 TBHP enable /disable (default disable) 11 PE0, PE1 Pull-high by bit 12 PE0, PE1 wake-up by bit 13 PB0~7 VDD :5V (default) 14 PB0~7 VDD :V33O V33O regulator output Rev. 1.10 HT82B40R/HT82B40A Read/Write Option R Store current table read bit11~bit8 data Options 34 Functions September 4, 2009 ...
Page 35
... Application Circuits Crystal or Ceramic Resonator for Multiple I/O Applications for HT82B40R Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. Components with * are used for EMC issue. ...
Page 36
... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.10 HT82B40R/HT82B40A subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
Page 37
... DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.10 HT82B40R/HT82B40A Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
Page 38
... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 HT82B40R/HT82B40A Description 38 Cycles Flag Affected ...
Page 39
... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.10 HT82B40R/HT82B40A 39 September 4, 2009 ...
Page 40
... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.10 HT82B40R/HT82B40A addr 40 September 4, 2009 ...
Page 41
... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82B40R/HT82B40A September 4, 2009 ...
Page 42
... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.10 HT82B40R/HT82B40A addr 42 September 4, 2009 ...
Page 43
... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.10 Stack Stack Stack [m]. 0~6) 43 HT82B40R/HT82B40A September 4, 2009 ...
Page 44
... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.10 [m]. 0~6) 44 HT82B40R/HT82B40A September 4, 2009 ...
Page 45
... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.10 [ HT82B40R/HT82B40A September 4, 2009 ...
Page 46
... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.10 0 [m] [ HT82B40R/HT82B40A September 4, 2009 ...
Page 47
... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.10 HT82B40R/HT82B40A [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 47 September 4, 2009 ...
Page 48
... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.10 HT82B40R/HT82B40A 48 September 4, 2009 ...
Page 49
... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.335 0.049 0.025 0.004 0.015 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 8.51 1.24 0.64 0.10 0.38 0. HT82B40R/HT82B40A Max. 0.244 0.158 0.012 0.347 0.065 0.010 0.050 0.010 8 Max. 6.20 4.01 0.30 8.81 1.65 0.25 1.27 0.25 8 September 4, 2009 ...
Page 50
... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.386 0.054 0.025 0.004 0.022 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 9.80 1.37 0.64 0.10 0.56 0. HT82B40R/HT82B40A Max. 0.244 0.157 0.012 0.394 0.060 0.010 0.028 0.010 8 Max. 6.20 3.99 0.30 10.01 1.52 0.25 0.71 0.25 8 September 4, 2009 ...
Page 51
... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.395 0.291 0.008 0.613 0.085 0.025 0.004 0.025 0.004 0 Dimensions in mm Min. Nom. 10.03 7.39 0.20 15.57 2.16 0.64 0.10 0.64 0. HT82B40R/HT82B40A Max. 0.420 0.299 0.012 0.637 0.099 0.010 0.035 0.012 8 Max. 10.67 7.59 0.30 16.18 2.51 0.25 0.89 0.30 8 September 4, 2009 ...
Page 52
... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.028 0.000 0.008 0.010 0.197 0.197 0.026 0.118 0.118 0.018 0.008 Dimensions in mm Min. Nom. 0.70 0.00 0.20 0.25 5.00 5.00 0.65 3.00 3.00 0.45 0.20 52 HT82B40R/HT82B40A Max. 0.031 0.002 0.014 0.126 0.126 0.026 Max. 0.80 0.05 0.35 3.20 3.20 0.65 September 4, 2009 ...
Page 53
... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.028 0.000 0.008 0.007 0.197 0.197 0.020 0.049 0.049 0.012 Dimensions in mm Min. Nom. 0.70 0.00 0.20 0.18 5.00 5.00 0.50 1.25 1.25 0.30 53 HT82B40R/HT82B40A Max. 0.031 0.002 0.012 0.128 0.128 0.020 Max. 0.80 0.05 0.30 3.25 3.25 0.50 September 4, 2009 ...
Page 54
... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 HT82B40R/HT82B40A Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 0.1 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 32.2 38.2 0.2 54 September 4, 2009 ...
Page 55
... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 HT82B40R/HT82B40A Dimensions in mm +0.3/-0.1 16.0 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 9.0 0.1 2.3 0.1 0.30 0.05 13.3 0.1 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2 ...
Page 56
... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 HT82B40R/HT82B40A Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.10 14.2 0.1 2 Min. +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 12.0 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 0.1 56 September 4, 2009 ...
Page 57
... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 HT82B40R/HT82B40A 57 September 4, 2009 ...