ht82b60r Holtek Semiconductor Inc., ht82b60r Datasheet
ht82b60r
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ht82b60r Summary of contents
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... Integrated 1.5k resistor between V33O and USBPDN pins for USB applications General Description The HT82B60R is a high performance, RISC architec- ture microcontroller device specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibil- ity, timer functions, integrated USB interface, serial in- ...
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... Block Diagram Pin Assignment Rev. 1.00 2 HT82B60R July 22, 2010 ...
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... USBPDN line. USB function is controlled by software control regis- ters. Schmitt trigger reset input. Active low Digital negative power supply, ground Digital positive power supply 3.3V regulator output +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 3 HT82B60R July 22, 2010 ...
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... V33O by option for PB 0.8V DDIO 0. 2 =70mA 3.0 V33O 5V V =0. =3. LCDC. RSEL[1:0]=00 17.5 LCDC. RSEL[1:0]= LCDC. RSEL[1:0]=10 70 LCDC. RSEL[1:0]=11 140 5V No load 0.475 HT82B60R Ta=25 C Typ. Max. Unit 5 400 0.8 V 0.3V V DDIO 0. DDIO ...
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... WDT Time_out in Power Down Mode = 1/ f Trimmed for 5V operation using factory trim values. Frequency Trim to 12MHz 3% Rev. 1.00 Test Conditions V Conditions DD 5V 4.0V~ 10.80 5.5V 3.0~ 10.56 4.0V 4.2~ 11.82 5. OSCsetup 256 WDTS + t RCSYS WDT 256 WDTS + t RCSYS OST 5 HT82B60R Ta=25 C Min. Typ. Max. Unit kHz 1/f 1024 RCSYS 75 300 ns t 1024 SYS 5 ms 12.00 13.20 MHz 12.00 13.44 MHz 12.00 12 ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. System Clocking and Pipelining Instruction Fetching 6 HT82B60R July 22, 2010 ...
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... Program Counter + 2 *11 * #11 # Program Counter @7~@0: PCL bits S12~S0: Stack register bits 7 HT82B60R * ...
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... Program Memory Structure Table Location Bits PC9 PC8 @ Table Location @7~@0: Table Pointer TBLP bits 8 HT82B60R 2 C interrupt bus, dependent upon which July 22, 2010 ...
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... TABRDC [m] instruc- tion is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] in- struction is executed. Table Read - TBLP/TBHP 9 HT82B60R July 22, 2010 ...
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... Data Memory. Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the SET [m].i and CLR [m].i with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP. 10 HT82B60R July 22, 2010 ...
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... When any operation to the relevant Indirect Ad- dressing Registers is carried out, the actual address that the microcontroller is directed to, is the address speci- fied by the related Memory Pointer. MP0 can only ac- cess data in Bank 0 while MP1 can access both banks. 11 HT82B60R July 22, 2010 ...
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... The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT in- struction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. 12 HT82B60R July 22, 2010 ...
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... During program initialisation important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these regis- ters is the ability to directly program single bits using the 13 HT82B60R July 22, 2010 ...
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... When the corresponding bit of the control register is written the I/O pin will be setup as an output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program 14 HT82B60R July 22, 2010 ...
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... After a reset, all of the data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the PAC, PBC, Input/Output Ports 15 HT82B60R July 22, 2010 ...
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... It must be note when using instructions to preload data into the low byte timer register, namely TMR1L, the data will only be placed in a low byte buffer and not directly into the low byte timer register. The actual transfer of the data into 16 HT82B60R July 22, 2010 ...
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... Timer/Event Counter 0 Structure 16-bit Timer/Event Counter 1 Structure Timer/Event Counter 0 Control Register Timer/Event Counter 1 Control Register Rev. 1.00 17 HT82B60R July 22, 2010 ...
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... T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode Timer Mode Timing Chart Event Counter Mode Timing Chart 18 HT82B60R Bit7 Bit6 used as the inter- SYS Bit7 Bit6 ...
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... Timer/Event Counter is full and overflows, an interrupt Bit7 Bit6 signal is generated and the Timer/Event Counter will re- load the value already loaded into the preload register 1 1 and continue counting. The interrupt can be disabled by 19 HT82B60R /4 is used as the inter- SYS July 22, 2010 ...
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... Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter the timer mode, which uses the internal system clock as the clock source. 20 HT82B60R July 22, 2010 ...
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... EMI bit should be set after entering the rou- tine, to allow interrupt nesting. If the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. 21 HT82B60R July 22, 2010 ...
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... Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H/0CH, will take place. When the in- terrupt is serviced, the timer interrupt request flag, T0F/T1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. 22 HT82B60R July 22, 2010 ...
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... Rev. 1.00 INTC0 Register INTC0 Register 23 HT82B60R July 22, 2010 ...
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... Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing a 24 HT82B60R July 22, 2010 ...
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... Pro- gram Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set Refer to the A.C. Characteristics for t details. SST WDT Time-out Reset during Normal Operation Timing Chart 25 HT82B60R value can be se- July 22, 2010 ...
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... HT82B60R USB Reset USB Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu ...
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... HT82B60R USB Reset USB Reset (Normal) (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ...
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... Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. 28 HT82B60R July 22, 2010 ...
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... If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recom- mended, since the HALT will stop the system clock. Watchdog Timer 29 HT82B60R July 22, 2010 ...
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... As the device has a remote wake up function it can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of the USC register). Once the USB Host receives a wake-up signal from the devices, it will send a Resume signal to the device. The timing is as follows: 30 HT82B60R July 22, 2010 ...
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... Otherwise it is always read MODE_CTRL 0=0, and MODE_CTRL 1=1, the device is configured as a USB interface. Both the USBPDN and USBPDP is driven by the SIE of the HT82B60R. The user can only write or read the USB data through the corresponding FIFO. Both the MODE_CTRL 0~1 de- fault is 0 ...
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... This bit is used to adjust the system clock for the USB mode for temperature changes. In the Power-down Mode this bit should be set high to reduce power consumption. 7 CLK_adj R/W 0: enable (default) 1: disable Rev. 1.00 Function USR (21H) Register Function SCC (22H) Register 32 HT82B60R July 22, 2010 ...
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... Bit 2 Reserved Pipe 3 Pipe 2 Pipe 3 Pipe 2 Pipe 3 Pipe 2 Pipe 3 Pipe 2 Read/Write R/W R/W R/W R/W R/W USB_STAT (40H) Register Table Description USB_STAT Function Table 33 HT82B60R Default Bit 1 Bit 0 Value Pipe 1 Pipe 0 00001111 Pipe 1 DATA0 00001110 Pipe 1 Pipe 0 00001110 Pipe 1 Pipe 0 00000000 Register Address 01000000B July 22, 2010 ...
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... PC Host IN or OUT token. Only for Endpoint0 1: has only USB interrupt, data is transmitted to the PC host or data is received from the PC NMI R/W Host 0: always has USB interrupt if the USB accesses FIFO0 Default 0 Rev. 1.00 Read/Write R/W R/W R/W SIES (45H) Register Table Description SIES Function Table 34 HT82B60R Register Address 01000001B July 22, 2010 ...
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... HT82B60R Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0 ...
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... LCD panel which is being used. The bias resistor choice is imple- mented using the RSEL0 and RSEL1 bits in the LCDC register RSEL0 LCDEN COM3EN COM2EN R/W R/W R LCD Register 36 HT82B60R Functions Pin O/P PCC Function Level COM ...
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... SPI interface is carried out in a slave/master mode with all data transfer initiations be- ing implemented by the master. The Master also con- trols the clock signal. As the device only contains a single SCS pin only one slave device can be utilised. 37 HT82B60R July 22, 2010 ...
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... SIMCTL2. Note that the SIMCTL1 register is only used 2 by the I C interface. Register I/O Status SIMCTL2 CSEN SPI SCS SPI 1 0 SPI 1 1 SPI SCS SPI Block Diagram 38 HT82B60R Function SIM interface or I/O pins Enable/Disable Enable/Disable Note I/O I/O I/O SCS not floating I/O SCS not floating July 22, 2010 ...
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... These two bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data trans- fer is executed otherwise an erroneous clock edge 39 HT82B60R SPI Master/Slave Clock Control and I2C Enable SPI Master ...
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... SIMDR register. After the data is received from the I bus, the microcontroller can read it from the SIMDR register. Any transmission or reception of data from 2 the I C bus must be made via the SIMDR register. 40 HT82B60R inter bus. 2 ...
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... SPI/I Rev. 1. Control Register - SIMCTL0 C Control Register - SIMCTL1 2 I SPI Control Register - SIMCTL2 41 HT82B60R July 22, 2010 ...
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... Rev. 1.00 SPI Master Mode Timing SPI Slave Mode Timing (CKEG=0) SPI Slave Mode Timing (CKEG=1) 42 HT82B60R July 22, 2010 ...
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... Rev. 1.00 SPI Transfer Control Flowchart Block Diagram 43 HT82B60R July 22, 2010 ...
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... Step 1 Write the slave address of the microcontroller to the I bus address register SIMAR. Step 2 Set the SIMEN bit in the SIMCTL0 register en- 2 able the I C bus. 44 HT82B60R 2 C bus, all de interrupt will 2 C bus, the 2 C July 22, 2010 ...
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... SIMCTL1 register should be set the SRW bit is low then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMCTL1 register should be set Slave Address Register - SIMAR 45 HT82B60R 2 C bus. The 2 C bus, ther efor e the 2 ...
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... I Rev. 1.00 C Communication Timing Diagram Bus ISR Flow Chart 46 HT82B60R July 22, 2010 ...
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... The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device is pow- ered down, this will disable the Peripheral Clock output. Peripheral Clock Block Diagram 47 HT82B60R July 22, 2010 ...
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... Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. Components with * are used for EMC issue. Rev. 1.00 48 HT82B60R July 22, 2010 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 49 HT82B60R July 22, 2010 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 50 HT82B60R Cycles Flag Affected AC, OV Note AC AC AC, OV ...
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... The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. 4. Configuration option TBHP option is enabled 5. Configuration option TBHP option is disabled Rev. 1.00 Description 51 HT82B60R Cycles Flag Affected 1 None Note 1 None 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 52 HT82B60R July 22, 2010 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 53 HT82B60R July 22, 2010 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82B60R July 22, 2010 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 55 HT82B60R July 22, 2010 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 56 HT82B60R July 22, 2010 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 57 HT82B60R July 22, 2010 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT82B60R July 22, 2010 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT82B60R July 22, 2010 ...
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... The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 60 HT82B60R July 22, 2010 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 61 HT82B60R July 22, 2010 ...
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... Symbol Rev. 1.00 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.335 0.049 0.025 0.004 0.015 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 8.51 1.24 0.64 0.10 0.38 0. HT82B60R Max. 0.244 0.158 0.012 0.347 0.065 0.010 0.050 0.010 8 Max. 6.20 4.01 0.30 8.81 1.65 0.25 1.27 0.25 8 July 22, 2010 ...
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... Symbol Rev. 1.00 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.386 0.054 0.025 0.004 0.022 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 9.80 1.37 0.64 0.10 0.56 0. HT82B60R Max. 0.244 0.157 0.012 0.394 0.060 0.010 0.028 0.010 8 Max. 6.20 3.99 0.30 10.01 1.52 0.25 0.71 0.25 8 July 22, 2010 ...
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... Symbol Rev. 1.00 Dimensions in inch Min. Nom. 0.395 0.291 0.008 0.613 0.085 0.025 0.004 0.025 0.004 0 Dimensions in mm Min. Nom. 10.03 7.39 0.20 15.57 2.16 0.64 0.10 0.64 0. HT82B60R Max. 0.420 0.299 0.012 0.637 0.099 0.010 0.035 0.012 8 Max. 10.67 7.59 0.30 16.18 2.51 0.25 0.89 0.30 8 July 22, 2010 ...
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... Symbol Rev. 1.00 Dimensions in inch Min. Nom. 0.028 0.000 0.008 0.007 0.197 0.197 0.020 0.049 0.049 0.012 Dimensions in mm Min. Nom. 0.70 0.00 0.20 0.18 5.00 5.00 0.50 1.25 1.25 0.30 65 HT82B60R Max. 0.031 0.002 0.012 0.128 0.128 0.020 Max. 0.80 0.05 0.30 3.25 3.25 0.50 July 22, 2010 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 0.1 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 32.2 38.2 0.2 66 HT82B60R July 22, 2010 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm +0.3/-0.1 16.0 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 9.0 0.1 2.3 0.1 0.30 0.05 13.3 0.1 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 67 HT82B60R July 22, 2010 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.10 14.2 0.1 2 Min. +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 12.0 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 0.1 68 HT82B60R July 22, 2010 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 69 HT82B60R July 22, 2010 ...