ht827a0 Holtek Semiconductor Inc., ht827a0 Datasheet - Page 15

• Manufacturer Part Number: ht827a0
• Description: 8-bit Microcontroller With Voice Rom
• Manufacturer: Holtek Semiconductor Inc.

WDT prescaler, a longer time-out period can be
attained. Writing data to WS2, WS1 and WS0
(bits 2, 1 and 0 of WDTS) can derive different
time-out periods. If WS2, WS1 and WS0 are all
equal to 1, the division ratio is up to 1:128, and
the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock
may still come from an instruction clock. It oper-
ates in the same manner except that WDT may
stop counting and loses its protecting purpose in
the HALT state. In this situation the logic can
only be re-initialized by external logic. The high
nibble and bit 3 of WDTS are reserved for user¢s
defined flags. The programmer may use these
flags to indicate some specified statuses.
The on-chip RC oscillator (WDT OSC) is
strongly recommended if the device operates in
a noisy environment, since the HALT function
will stop the system clock.
Overflow of the WDT under a normal operation
initializes a ²chip reset² and sets the status bit
²TO². It will initialize a ²warm reset², and only
PC and SP are reset to zero in the HALT mode.
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS register
WS0
0
1
0
1
0
1
0
1
Division Ratio
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
Watchdog timer
15
To clear the contents of WDT (including the
WDT prescaler), three methods are adopted,
namely, external reset (a low level to RES),
software instructions, and ²HALT² instruction.
The software instructions include ²CLR WDT²
and the other sets - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, by
mask option only one can be active at a time -
²CLR WDT times selection option². If ²CLR
WDT² is chosen (i.e., CLRWDT times equal
one), any execution of the ²CLR WDT² instruc-
tion will clear WDT. In the case that ²CLR
WDT1² and ²CLR WDT2² are selected (i.e.,
CLRWDT times equal two), these two instruc-
tions must be executed to clear WDT; otherwise
WDT may reset the chip as a result of time-out.
Power down operation - HALT
The HALT mode is initialized by the ²HALT²
instruction and results in the following:
·
·
·
·
·
The system can quit the HALT mode by an exter-
nal reset, interrupt, external falling edge signal
on port A or WDT overflow. An external reset
leads to device initialization and a WDT overflow
performs a ²warm reset². The reason for chip re-
The system oscillator is turned off but the
WDT oscillator still keeps running (if the
WDT oscillator is selected).
The contents of the on-chip RAM and regis-
ters remain unchanged.
The WDT and WDT prescaler are cleared and
re-counted (if the clock of WDT is from the
WDT oscillator).
All the I/O ports maintain their original
statuses.
The PD flag is set and the TO flag cleared.
March 15, 2000
HT827A0