as7c331mntf32a Alliance Memory, Inc, as7c331mntf32a Datasheet

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as7c331mntf32a

Manufacturer Part Number
as7c331mntf32a
Description
3.3v 32/36 Flowthrough Sram With
Manufacturer
Alliance Memory, Inc
Datasheet
Logic block diagram
Selection guide
Features
• Organization: 1,048,576 words × 32 or 36 bits
• NTD
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
December 2004
12/23/04, v 1.2
architecture for efficient bus operation
A[19:0]
CE1
CE2
CE0
DQ[a,b,c,d]
ADV / LD
3.3V 1M × 32/36 Flowthrough SRAM with NTD
BWb
BWd
BWa
BWc
LBO
R/W
ZZ
CLK
CEN
32/36
20
D
D
Control
Burst logic
Address
Register
register
logic
CLK
Input
Data
CLK
Alliance Semiconductor
CLK
Q
Q
140
325
-75
8.5
7.5
90
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
20
OE
32/36
addr. registers
D
CLK
Write delay
®
300
130
-85
8.5
10
90
32/36
Q
OE
32/36
CLK
Output
Buffer
32/36
1M x 32/36
DQ[a,b,c,d]
20
SRAM
32/36
Array
TM
Copyright © Alliance Semiconductor. All rights reserved.
AS7C331MNTF32A
AS7C331MNTF36A
275
130
-10
12
10
90
DDQ
P. 1 of 18
Units
mA
mA
mA
ns
ns

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as7c331mntf32a Summary of contents

Page 1

... Q D Address register Burst logic CLK D Write delay addr. registers CLK Control logic CLK 32/36 32/36 Data D Q Input Register CLK OE -75 8.5 7.5 325 140 90 Alliance Semiconductor AS7C331MNTF32A AS7C331MNTF36A TM DDQ Q 20 CLK 1M x 32/36 SRAM Array 32/36 32/36 32/36 Output Buffer OE 32/36 DQ[a,b,c,d] -85 -10 Units 8 300 275 mA 130 ...

Page 2

... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C331MNTF32A/36A Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...

Page 3

... DQd4 25 DQd5 V 26 SSQ V 27 DDQ 28 DQd6 29 DQd7 30 NC/DQPd Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration. 12/23/04, v 1.2 ® TQFP 14 x 20mm Alliance Semiconductor AS7C331MNTF32A/36A 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 73 DQb3 72 ...

Page 4

... Functional Description The AS7C331MNTF32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × bits and incorporates a LATE Write. This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD write operation that improves bandwidth over flowthrough burst devices normal flowthrough burst device, the write data, command, and address are all applied to the device on the same clock edge ...

Page 5

... SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 12/23/04, v 1.2 ® Description or left floating, device follows interleaved Burst order. When DD is met. After entering SNOOZE MODE, all inputs except ZZ ZZI Alliance Semiconductor AS7C331MNTF32A/36A ...

Page 6

... External NOP/WRITE ABORT (Begin Burst) High Next Current enables WRITEs to byte “b” (DQb pins); Alliance Semiconductor AS7C331MNTF32A/36A Linear burst order LBO = ...

Page 7

... Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C331MNTF32A/36A Burst Dsel Burst Burst Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 – –65 +150 o –65 +135 Max Unit 3 ...

Page 8

... < Max Deselected < 0.2V, I SB1 ≤ 0.2V or ≥ V all ≥ V Deselected Max I SB2 ≤ ≥ V all Alliance Semiconductor AS7C331MNTF32A/36A Min Max Unit -2 2 µA DD < µA DDQ +0.3 DDQ -0.3** 0 ...

Page 9

... CENH t 2.0 – 2.0 ADVS t 0.5 – 0.5 ADVH t 2 – 2 PDS t 2 – 2 PUS Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C331MNTF32A/36A -10 1 Unit Notes Min Max – 12 – ns – – 4.0 ns – 2.5 – ns 2,3,4 – 2.5 – – 0 – ns 2,3,4 – 4.0 ns 2,3,4 – ...

Page 10

... Falling input HZOE Q(A2) Q(A2Y‘01) Q(A2Y‘10) BURST BURST READ BURST READ Q(A2) READ READ Q(A2Ý11) Q(A2Ý01) Q(A2Ý10) Alliance Semiconductor AS7C331MNTF32A/36A Undefined t CYC A3 Q(A2Y‘11) Q(A3) Q(A3Y‘01) STALL READ BURST Q(A3) READ Q(A3Ý01 ...

Page 11

... ADV/LD OE D(A1) Din t HZOE Dout Q(n-1) WRITE DSEL Command D(A1) 12/23/04, v 1.2 ® D(A2) D(A2Y‘01) D(A2Y‘10) BURST BURST WRITE BURST WRITE WRITE D(A2) WRITE D(A2Ý10) D(A2Ý11) D(A2Ý01) Alliance Semiconductor AS7C331MNTF32A/36A t CYC D(A3) D(A2Y‘11) D(A3Y‘01) STALL WRITE BURST D(A3) WRITE D(A3Ý01 ...

Page 12

... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. 12/23/04, v 1.2 ® HZOE LZC OH D(A2) Q(A3) Q(A4) D(A2Ý01) BURST BURST READ READ WRITE READ Q(A3) Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C331MNTF32A/36A t CYC HZC D(A5) Q(A6) D(A7) Q(A4Ý01) t LZOE WRITE READ WRITE DSEL D(A5) Q(A6) D(A7 ...

Page 13

... BURST Command Q(A1) Q(A1 Ý Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 12/23/04, v 1.2 ® Q(A1Ý10) Q(A1Ý01) STALL DSEL BURST BURST 01) Q(A1 10) DSEL Ý Alliance Semiconductor AS7C331MNTF32A/36A A2 A3 D(A2) BURST WRITE WRITE BURST NOP NOP D(A2) D(A2 10) Ý D(A2 01) D(A3) Ý ...

Page 14

... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 12/23/04, v 1.2 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C331MNTF32A/36A Normal operation Cycle ...

Page 15

... L for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC IL Alliance Semiconductor AS7C331MNTF32A/36A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) ...

Page 16

... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 12/23/04, v 1.2 ® Alliance Semiconductor AS7C331MNTF32A/36A b e α ...

Page 17

... Ordering information Package & –75 Width AS7C331MNTF32A-75TQC TQFP x32 AS7C331MNTF32A-75TQI AS7C331MNTF36A-75TQC TQFP x36 AS7C331MNTF36A-75TQI Notes: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C331MNTF32A-75TQCN) Part numbering guide AS7C Alliance Semiconductor SRAM prefix 2. Operating voltage 3.3V 3 ...

Page 18

... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C331MNTF32A/36A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C331MNTF32A AS7C331MNTF36A Document Version: v 1.2 ...

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