as7c331mpfd18a Alliance Memory, Inc, as7c331mpfd18a Datasheet

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as7c331mpfd18a

Manufacturer Part Number
as7c331mpfd18a
Description
3.3v Pipelined Burst Synchronous Sram
Manufacturer
Alliance Memory, Inc
Datasheet
Logic block diagram
Selection guide
Features
• Organization: 1,048,576 x18 bits
• Fast clock speeds to 166MHz
• Fast clock to data access: 3.4/3.8 ns
• Fast OE access time: 3.4/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available 100-pin TQFP package
February 2005
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
2/10/05, v. 1.3
A[19:0]
ADSC
ADSP
GWE
BWE
ADV
BW
CLK
BW
CE0
CE1
CE2
OE
ZZ
3.3V 1M x 18 pipelined burst synchronous SRAM
b
a
Power
down
Alliance Semiconductor
20
CLK
CS
D
CLK
CS
CLR
D
D
D
D
CLK
CLK
CE
CLK
CLK
Byte Write
Byte Write
Address
register
registers
registers
register
register
Enable
Enable
delay
DQb
DQa
Burst logic
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3 V core power supply
• 2.5 V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Common data inputs and data outputs
• Snooze mode for reduced power-standby
Q
Q
Q
Q
Q
LBO
-166
166
290
3.4
90
60
6
20
®
18
20
OE
CLK
registers
Output
2
18
1M x 18
Memory
18
DQ[a,b]
array
-133
133
270
3.8
7.5
CLK
80
60
registers
18
Input
Copyright © Alliance Semiconductor. All rights reserved.
AS7C331MPFD18A
DDQ
Units
MHz
mA
mA
mA
ns
ns
1 of 19

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as7c331mpfd18a Summary of contents

Page 1

... D Q DQa Byte Write registers CLK D Q Enable register CE CLK D Q Enable Power delay down register CLK -166 6 166 3.4 290 90 60 Alliance Semiconductor AS7C331MPFD18A DDQ Memory 20 array Input Output registers registers CLK CLK 18 DQ[a,b] -133 Units 7.5 ns 133 MHz 3.8 ns 270 mA ...

Page 2

... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C331MPFD18A Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...

Page 3

... V 20 DDQ V 21 SSQ DQb6 22 DQb7 23 DQPb SSQ V 27 DDQ 2/10/05, v. 1.3 ® TQFP 14 × Alliance Semiconductor AS7C331MPFD18A DDQ V 76 SSQ NC 75 DQPa 74 DQa7 73 DQa6 SSQ V 70 DDQ DQa5 69 DQa4 ...

Page 4

... WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). • Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C331MPFD18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package. ...

Page 5

... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 2/10/05, v. 1.3 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ is SB2 ZZI Alliance Semiconductor AS7C331MPFD18A . The duration of SB2 ...

Page 6

... Din, High-Z X High Starting Address First Increment Second Increment Third Increment Alliance Semiconductor AS7C331MPFD18A BWb Linear burst address (LBO = ...

Page 7

... Alliance Semiconductor AS7C331MPFD18A CLK Operation Deselect Deselect Deselect Deselect Deselect External Begin read External Begin read External ...

Page 8

... T –65 bias Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C331MPFD18A Max Unit +4 0 0.5 V DDQ 1 +150 C o +135 C Max Unit 3.465 V 3.465 Max Unit 3 ...

Page 9

... Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected Max DD ≤ ≥ V all Alliance Semiconductor AS7C331MPFD18A Min Max Unit -2 2 µA DD < µA DDQ +0.3 DDQ -0.3** 0 ...

Page 10

... CSH t 1.5 ADVS t 1.5 ADSPS t 1.5 ADSCS t 0.5 ADVH t 0.5 ADSPH t 0.5 ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C331MPFD18A –166 –133 Max Min Max Unit Notes – 166 – 133 MHz 6 – 7.5 – ns – 3.4 – 3.8 ns – 3.4 – 3 – 0 – – ...

Page 11

... ADV inserts wait states HZOE t OH Q(A2) Q(A2Ý01) Q(A2Ý10) Read Burst Burst Suspend Burst Q(A2) Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C331MPFD18A Undefined A3 t HZC Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Read Burst Burst Burst Q(A3) Read Read Read DSEL* Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...

Page 12

... CL ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) ADV Suspend Read Suspend Burst Write Q(A2) Write Write D D(A 2Ý01 ) D(A 2Ý01 ) D(A 2Ý10 ) Alliance Semiconductor AS7C331MPFD18A t t ADSCS ADSCH ADVS ADVH D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...

Page 13

... ADVH ADVS D(A2 HZOE LZOE t LZC Q(A1) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C331MPFD18A Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Burst Burst Burst Read Read Read Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...

Page 14

... GWE t t CSS CSH CE0,CE2 CE1 ADV LZOE Q(A1) Dout Din READ READ Q(A1) Q(A2) 2/10/05, v. 1.3 ® t CYC HZOE Q(A2) Q(A3) Q(A4 D(A5) D(A6) READ READ WRITE Q(A3) Q(A4) D(A5) Alliance Semiconductor AS7C331MPFD18A LZOE Q(A8 D(A7) READ WRITE WRITE READ Q(A9) D(A7) D(A6) Q(A8 Q(A9 ...

Page 15

... Dout Q(A1 supply S READ USPEND READ Q(A1) Q(A1) 2/10/05, v. 1.3 ® HZC t PUS t PDS ZZ Recovery Cycle ZZ Setup Cycle t ZZI t RZZI I SB2 Sleep State Alliance Semiconductor AS7C331MPFD18A t CYC D(A2) t HZOE D(A2(Ý01)) Normal Operation Mode READ USPEND Q(A2) WRITE TINUE D(A2) WRITE D( Ý01) ...

Page 16

... I/ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC is measured as low below VIL Alliance Semiconductor AS7C331MPFD18A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω /2 DDQ GND *including scope and jig capacitance ...

Page 17

... Package dimensions 100-pin TQFP (quad flat pack) TQFP Min Max c A1 0.05 0.15 A2 1.35 1. 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 2/10/05, v. 1.3 ® α Alliance Semiconductor AS7C331MPFD18A ...

Page 18

... Ordering information Width Package & TQFP x18 Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C331MPFD18A-166TQCN) Part numbering guide AS7C Alliance Semiconductor SRAM prefix 2. Operating voltage 3.3V 3. Organization Pipelined mode 5. Deselect Double cycle deselect 6 ...

Page 19

... Alliance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C331MPFD18A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number:AS7C331MPFD18A Document Version: v. 1.3 ...

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