as7c31026b Alliance Memory, Inc, as7c31026b Datasheet - Page 5

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as7c31026b

Manufacturer Part Number
as7c31026b
Description
3.3 V 64k X 16 Cmos Sram
Manufacturer
Alliance Memory, Inc
Datasheet

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Read waveform 2 (OE, CE, UB, LB controlled)
Write cycle (over the operating range)
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Write recovery time
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Byte select low to end of write
3/26/04, v 1.3
Address
LB, UB
Data
OE
CE
IN
Parameter
Symbol
t
t
OLZ
BLZ
t
t
t
t
t
t
t
t
t
t
t
t
WC
CW
AW
WR
DW
OW
BW
WP
AH
DH
WZ
AS
Alliance Semiconductor
t
LZ
11
Min Max Min Max Min Max Min
10
8
8
0
7
0
0
5
0
1
7
t
t
ACE
-10
AA
t
t
OE
BA
5
3,6,8,9
12
9
9
0
8
0
0
6
0
1
8
t
-12
RC
®
6
15
10
10
Data valid
0
9
0
0
8
0
1
9
-15
7
20
12
12
12
10
0
0
0
0
2
9
t
OH
t
-20
HZ
t
t
Max
OHZ
BHZ
8
AS7C31026B
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P. 5 of 10
Notes
4, 5
4, 5
5

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