as7c31026c Alliance Memory, Inc, as7c31026c Datasheet - Page 2

• Manufacturer Part Number: as7c31026c
• Description: 3.3 V 64k X 16 Cmos Sram
• Manufacturer: Alliance Memory, Inc

Functional description
The AS7C31026C is a 3V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (t
performance applications.
When CE is high, the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip
enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle
2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable
(OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31026C is packaged in
common industry standard packages
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key:
Truth table
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with VCC applied
DC current into outputs (low)
9/20/06, v 2.0
CE
H
L
L
L
L
L
L
L
L
H = high, L = low, X = don’t care.
CC
WE
relative to GND
X
H
H
H
H
X
L
L
L
Parameter
OE
X
X
X
X
H
X
L
L
L
.
AA
LB
X
H
H
X
H
L
L
L
L
, t
RC
, t
WC
Alliance Memory
) of 12 ns with output enable access times (t
UB
Symbol
X
H
H
X
H
L
L
L
L
T
I
T
V
V
OUT
P
bias
stg
D
t1
t2
I/O0–I/O7
High Z
High Z
High Z
High Z
D
D
D
D
OUT
OUT
®
IN
IN
–0.50
–0.50
Min
–55
–55
–
–
I/O8–I/O15
High Z
High Z
High Z
High Z
D
D
D
D
OUT
OUT
IN
IN
V
OE
Write I/O0–I/O15 (I
Write I/O8–I/O15 (I
CC
Read I/O0–I/O15 (I
Read I/O8–I/O15 (I
Write I/O0–I/O7 (I
+4.60
Read I/O0–I/O7 (I
+125
+125
Max
1.25
Output disable (I
Standby (I
) of 6 ns are ideal for high-
50
AS7C31026C
+0.50
Mode
SB
), I
P. 2 of 10
SBI
CC
CC
CC
CC
CC)
Unit
CC
CC
mA
)
°C
°C
)
W
V
V
)
)
)
)
)