as7c3256a Alliance Memory, Inc, as7c3256a Datasheet - Page 6

• Manufacturer Part Number: as7c3256a
• Description: 3.3v 32k X 8 Cmos Sram Common I/o
• Manufacturer: Alliance Memory, Inc

4/23/04; v.2.0
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.
- Output load: see Figure B
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+3.0V
GND
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B.
These parameters are specified with CL = 5pF, as in Figures B. Transition is measured
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10%
CC
Figure A: Input pulse
90%
power-up, a pull-up resistor to V
2 ns
90%
10%
CC
Alliance Semiconductor
on CE is required to meet I
Figure B: Output load
D
out
350
Ω
SB
®
specification.
+3.3V
320
C
GND
±
13
500mV from steady-state voltage.
Ω
D
out
Thevenin equivalent
168
Ω
+1.72V
AS7C3256A
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